Maker Pro
Maker Pro

47uf decoupling caps?!

M

Mike Noone

Jan 1, 1970
0
Hi - I'm currently working on designing a board around the Acam TDC-GPX
time to digital converter chip. I've run into something which I found
to be incredibly odd. They reccomend 47uf caps on almost every single
vdd line. 12 in all. See page 54 (second to last page) of the datasheet
for the drawing I'm referring to:
http://www.acam.de/fileadmin/Download/pdf/English/DB_GPX_e.pdf

They reccomend use of Taiyo-Yuden LMK325BJ476MM, which is a 1210 47uf
cap available at digikey at the price of $34.10/10 caps. Thus for a
single board I would be using about $40 in just decoupling caps!!

Typically, when I design a board, I put a .1uf 0603 ceramic on every
single supply pin of every IC, and then a single 10uf tantalum/ic on
the more sensitive ICs. My understanding was that this was more or less
the standard way to deal with decoupling.

So anyways - I'm starting to lay out this board - and these 12 1210s
are really getting in my way. They are making my life very difficult.
I'm trying to keep this as just a 2 layer board - but I'm not sure if I
can do it with all these damn 1210s all over the place.

My question is this: are such huge capacitors necessary? Are they even
worth it? The sales engineer for the distributor we purchased these
chips through didn't seem to have a good idea one way or the other. My
personal understanding was that it was better to have small but very
low esr caps on the supply pins, as opposed to really large capacity,
higher esr caps like these 1210s.

Thanks for any comments or suggestions,

-Mike
 
P

PeteS

Jan 1, 1970
0
Mike said:
Hi - I'm currently working on designing a board around the Acam TDC-GPX
time to digital converter chip. I've run into something which I found
to be incredibly odd. They reccomend 47uf caps on almost every single
vdd line. 12 in all. See page 54 (second to last page) of the datasheet
for the drawing I'm referring to:
http://www.acam.de/fileadmin/Download/pdf/English/DB_GPX_e.pdf

They reccomend use of Taiyo-Yuden LMK325BJ476MM, which is a 1210 47uf
cap available at digikey at the price of $34.10/10 caps. Thus for a
single board I would be using about $40 in just decoupling caps!!

Typically, when I design a board, I put a .1uf 0603 ceramic on every
single supply pin of every IC, and then a single 10uf tantalum/ic on
the more sensitive ICs. My understanding was that this was more or less
the standard way to deal with decoupling.

So anyways - I'm starting to lay out this board - and these 12 1210s
are really getting in my way. They are making my life very difficult.
I'm trying to keep this as just a 2 layer board - but I'm not sure if I
can do it with all these damn 1210s all over the place.

My question is this: are such huge capacitors necessary? Are they even
worth it? The sales engineer for the distributor we purchased these
chips through didn't seem to have a good idea one way or the other. My
personal understanding was that it was better to have small but very
low esr caps on the supply pins, as opposed to really large capacity,
higher esr caps like these 1210s.

Thanks for any comments or suggestions,

-Mike

Certainly seems overkill. Looking at the Icc specs, I would think you
would be fine with your normal technique, but of course this advice is
worth what you have paid for it :)

I would note that smaller caps give better high frequency decoupling
anyway.

Cheers

PeteS
 
R

rickman

Jan 1, 1970
0
Mike said:
Hi - I'm currently working on designing a board around the Acam TDC-GPX
time to digital converter chip. I've run into something which I found
to be incredibly odd. They reccomend 47uf caps on almost every single
vdd line. 12 in all. See page 54 (second to last page) of the datasheet
for the drawing I'm referring to:
http://www.acam.de/fileadmin/Download/pdf/English/DB_GPX_e.pdf

They reccomend use of Taiyo-Yuden LMK325BJ476MM, which is a 1210 47uf
cap available at digikey at the price of $34.10/10 caps. Thus for a
single board I would be using about $40 in just decoupling caps!!

Typically, when I design a board, I put a .1uf 0603 ceramic on every
single supply pin of every IC, and then a single 10uf tantalum/ic on
the more sensitive ICs. My understanding was that this was more or less
the standard way to deal with decoupling.

So anyways - I'm starting to lay out this board - and these 12 1210s
are really getting in my way. They are making my life very difficult.
I'm trying to keep this as just a 2 layer board - but I'm not sure if I
can do it with all these damn 1210s all over the place.

My question is this: are such huge capacitors necessary? Are they even
worth it? The sales engineer for the distributor we purchased these
chips through didn't seem to have a good idea one way or the other. My
personal understanding was that it was better to have small but very
low esr caps on the supply pins, as opposed to really large capacity,
higher esr caps like these 1210s.

I find this a very interesting post. A month or so ago I took a
workshop in high speed digital circuit design and learned a lot about
power supply decoupling. Basically everything you may think you know
is wrong. This guy is a consultant with more years than I have and
that is a lot. His experience has pretty much all been in doing high
speed circuit board design and everything he said was supported by an
explanation of the theory, simulation data and actual board test
results. So it is hard to argue with him.

He has data that shows that the rule of thumb of 0.1 uF cap per power
pin is way far over kill. In fact, the real high speed decoupling is
done by the power planes alone. The high speed noise can not be
smoothed by the caps simply because of their intrinsic inductance.
Further when they couple with the power plane capacitance, they really
do create a parallel resonance which *increases* the impedance at
certain frequencies.

His approach is to use closely spaced power and ground planes to create
a low impedance path at high frequencies. Then use a few 0.1 caps, a
few more 0.01 caps and a few more 0.001 caps. Of course the smaller
the package the better, but it is important to use parts that do not
have *too low* a value of ESR. The ESR will not affect the performance
of the caps, but it will minimize the peak of the parallel resonances
between all the different parts.

I think if you were to do a simulation of the effect of using 47 uF
1210 caps you will find that they may work great below a couple of MHz,
but have way too high inductance to be useful at anything over 50 MHz
or so, perhaps much less. The point is that *all* capacitors have
enough parasitic inductance to be inductive at the frequencies of
interest. This in itself is not bad, but it means the impedance is
going up with frequency and larger caps really won't work well at all
for high frequency decoupling. They are only needed for low frequency
work and because of that it does not matter where you put them.
 
J

J.A. Legris

Jan 1, 1970
0
Mike said:
Hi - I'm currently working on designing a board around the Acam TDC-GPX
time to digital converter chip. I've run into something which I found
to be incredibly odd. They reccomend 47uf caps on almost every single
vdd line. 12 in all. See page 54 (second to last page) of the datasheet
for the drawing I'm referring to:
http://www.acam.de/fileadmin/Download/pdf/English/DB_GPX_e.pdf

They reccomend use of Taiyo-Yuden LMK325BJ476MM, which is a 1210 47uf
cap available at digikey at the price of $34.10/10 caps. Thus for a
single board I would be using about $40 in just decoupling caps!!

Typically, when I design a board, I put a .1uf 0603 ceramic on every
single supply pin of every IC, and then a single 10uf tantalum/ic on
the more sensitive ICs. My understanding was that this was more or less
the standard way to deal with decoupling.

So anyways - I'm starting to lay out this board - and these 12 1210s
are really getting in my way. They are making my life very difficult.
I'm trying to keep this as just a 2 layer board - but I'm not sure if I
can do it with all these damn 1210s all over the place.

My question is this: are such huge capacitors necessary? Are they even
worth it? The sales engineer for the distributor we purchased these
chips through didn't seem to have a good idea one way or the other. My
personal understanding was that it was better to have small but very
low esr caps on the supply pins, as opposed to really large capacity,
higher esr caps like these 1210s.

Thanks for any comments or suggestions,

-Mike

Are you sure you need such a high-performance device? This thing will
measure time durations with over 6 digits of precision at a resolution
of 27 pico-seconds, but only by regulating the power supply to
compensate the variable internal time delays, using a phase-locked loop
synchronized to a crystal oscillator! It is definitely not a "standard"
decoupling situation.

If you really need the precision you should be ready to shell out for
the caps, and for a multi-layer board too - the data sheet recommends a
ground plane.
 
A

Ancient_Hacker

Jan 1, 1970
0
Mike said:
Hi - I'm currently working on designing a board around the Acam TDC-GPX
time to digital converter chip. I've run into something which I found
to be incredibly odd. They reccomend 47uf caps on almost every single
vdd line. 12 in all. See page 54 (second to last page) of the datasheet
for the drawing I'm referring to:
http://www.acam.de/fileadmin/Download/pdf/English/DB_GPX_e.pdf


Wow. It all depends on what frequency range and impedance you want
the power supply to be able to supply.

Usually 47uF capacitors are going to be good for providing very low
impedances at relatively low frequencies. 47uF is going to be series
resonant and therefore useless above 100KHz to 1MHz or so. So they'd
be good in a say SMPS running at 50KHz and say 10 amps. But darn near
useless in the megahertz region.

Are you sure they didnt mean to write NANO-farads? But even 47nF is
going to resonate in the tens of MHz, which is fine for medium-speed
designs maybe, but not for anything exotic.

For the best bypassing, you need a layered approach, with like 1nF as
close as possible to the IC, then 10nF an inch away, then maybe 100nF
per row.

For sensitive designs yo have to ignore that very general rule-of-thumb
and analyze the power busses as an electrical network.

I'd look very carefully at the di/dt rates around the IC and outfit it
with capacitors capable of supplying those rates at the noise margins
you need. Just throwing big caps at it is not going to give you
optimum results.

For really fussy designs you even have to consider adding a smidgen of
series resistance with the caps, so the spike and noise energy gets
dissipated instead of ringing the parasitic LC networks.
 
M

Mike Noone

Jan 1, 1970
0
J.A. Legris said:
Are you sure you need such a high-performance device? This thing will
measure time durations with over 6 digits of precision at a resolution
of 27 pico-seconds, but only by regulating the power supply to
compensate the variable internal time delays, using a phase-locked loop
synchronized to a crystal oscillator! It is definitely not a "standard"
decoupling situation.

If you really need the precision you should be ready to shell out for
the caps, and for a multi-layer board too - the data sheet recommends a
ground plane.

Hi Joe - the precision of the TDC-GPX is necessary.

My question is whether or not they will improve things at all - if they
really are necessary. From what I know of decoupling, they will
decrease performance, not improve it. But like you said - it's not a
typical decoupling situation.

Thanks,

-Mike
 
A

Ancient_Hacker

Jan 1, 1970
0
OH, I should have looked at the datasheet first before typing.

This is no typical IC!

It's quite possible this IC needs those funny capacitors, as the Vcc
line isnt being used in a normal way-- they're modulating Vcc with the
voltage regulator! And they mention you better use the LM117, as
they're probably depending on some quirk of its characteristics..
Yipes.

And they may be specing those funny 47uF caps because that's what
worked for them. They're likely depending on some undocumented amount
of ESR of those caps to just so happen act as nice R-C dampers for
their modulated Vcc bus.

In a perfect world, they would have done a full-bore AC analysis and
shown it in the datasheet or app notes. Maybe they did or maybe they
didnt, or maybe the datasheet writer tossed out all the analysis and
detailed design info. Or maybe they just kept adding capacitors of
various sizes and types until the thing didnt oscillate any more.

When I see a spec sheet like this one, I usually think, very
interesting, but way too hairy for me.

BTW Are you up to speed on designing PC traces that can carry xx
picosecond risetimes without smearing and ringing? The chip is only
going to be able to do its job if you can deliver clean edges. This
means impedance compatible striplines or maybe micro-coax.

I'd ask those folks if they have a reference design PC board--
designing picosecond circuits is mighty hairy. Anything under 5 nsec
and I start to tremble.
 
J

John Larkin

Jan 1, 1970
0
Hi - I'm currently working on designing a board around the Acam TDC-GPX
time to digital converter chip. I've run into something which I found
to be incredibly odd. They reccomend 47uf caps on almost every single
vdd line. 12 in all. See page 54 (second to last page) of the datasheet
for the drawing I'm referring to:
http://www.acam.de/fileadmin/Download/pdf/English/DB_GPX_e.pdf

They reccomend use of Taiyo-Yuden LMK325BJ476MM, which is a 1210 47uf
cap available at digikey at the price of $34.10/10 caps. Thus for a
single board I would be using about $40 in just decoupling caps!!

Typically, when I design a board, I put a .1uf 0603 ceramic on every
single supply pin of every IC, and then a single 10uf tantalum/ic on
the more sensitive ICs. My understanding was that this was more or less
the standard way to deal with decoupling.

So anyways - I'm starting to lay out this board - and these 12 1210s
are really getting in my way. They are making my life very difficult.
I'm trying to keep this as just a 2 layer board - but I'm not sure if I
can do it with all these damn 1210s all over the place.

My question is this: are such huge capacitors necessary? Are they even
worth it? The sales engineer for the distributor we purchased these
chips through didn't seem to have a good idea one way or the other. My
personal understanding was that it was better to have small but very
low esr caps on the supply pins, as opposed to really large capacity,
higher esr caps like these 1210s.

Thanks for any comments or suggestions,

-Mike


See fig 9. This chip looks to be fairly sensitive to Vcc, which means
that jitter will be high if it's not bypassed pretty hard. And if it's
typical of this sort of chip, Icc will vary a lot with activity.

Things like this really deserve to be on multilayer boards. With
ps-resolution logic inputs and cmos outputs, it's not hard to add
enough noise, ground bounce, and power supply noise to wreck the time
resolution.

I'd suggest a 4 or 6-layer board with ground and power planes, and use
the big caps at first, until you can evaluate whether they're really
necessary in your application.

What are you making?

John
 
N

nospam

Jan 1, 1970
0
Mike Noone said:
Typically, when I design a board, I put a .1uf 0603 ceramic on every
single supply pin of every IC, and then a single 10uf tantalum/ic on
the more sensitive ICs. My understanding was that this was more or less
the standard way to deal with decoupling.

Well the TDC-GPX is far from a 'standard' chip. Acam also strongly
recommend against using switchmode power supplies for it.

Unless you are prepared to do the development work to determine how
different decoupling schemes affect the chip performance I would take their
recommendations seriously. You could of course ask Acam for more
recommendations.
So anyways - I'm starting to lay out this board - and these 12 1210s
are really getting in my way. They are making my life very difficult.
I'm trying to keep this as just a 2 layer board - but I'm not sure if I
can do it with all these damn 1210s all over the place.

I presume this isn't a cheap chip, the capacitors are not cheap, I don't
think I would trying to skimp on PCB layers to save a few bucks.

I also presume this is not your design and you are just doing PCB layout,
doesn't the designer have something to say about it?
--
 
B

Boris Mohar

Jan 1, 1970
0
Hi Joe - the precision of the TDC-GPX is necessary.

My question is whether or not they will improve things at all - if they
really are necessary. From what I know of decoupling, they will
decrease performance, not improve it. But like you said - it's not a
typical decoupling situation.

Thanks,

-Mike


Those caps are ceramic X7R ESR will be quite low.
 
J

John Larkin

Jan 1, 1970
0
I would note that smaller caps give better high frequency decoupling
anyway.

Why? ESL depends on case size, not capacitance.

John
 
M

Mike Noone

Jan 1, 1970
0
John said:
See fig 9. This chip looks to be fairly sensitive to Vcc, which means
that jitter will be high if it's not bypassed pretty hard. And if it's
typical of this sort of chip, Icc will vary a lot with activity.

Things like this really deserve to be on multilayer boards. With
ps-resolution logic inputs and cmos outputs, it's not hard to add
enough noise, ground bounce, and power supply noise to wreck the time
resolution.

I'd suggest a 4 or 6-layer board with ground and power planes, and use
the big caps at first, until you can evaluate whether they're really
necessary in your application.

What are you making?

John

Problem with multilayer boards is two fold:
1. the software I use can only do two layers, unless I want to buy the
full version (currently using free version of Cadsoft's Eagle)
2. multilayer boards are quite expensive. I currently get my boards
through advanced pcb with their student $33 each special program - $33
+ shipping for a 2 layer board with 5 day turn around. I expect cost
for a 4 or 6 layer board would be at least a couple hundred dollars.

Oddly enough - I'm making two different things, both will use this
board:
1. A device that can measure the time between pulses on a single line.
The pulses come in on this line every couple nanoseconds to
microseconds. The pulses are about 20-50ns long as I recall. By
measuring the time between them this device will be generating,
apparently, pure random data. It will be an integral part of a ultra
high speed random number generator for use in quantum cryptography. I
don't understand any of the quantum stuff - I'm just an EE guy.
2. scanning laser rangefinder. We'll be using it to do time of flight
measurements on pulses being sent by a laser that is on a rotating
gimbal so that it can do 3D scans of an area.

So I'm wondering - I was told that the only really sensitive lines are
the VDDC lines. Maybe it would be OK if I just used these caps on those
lines, and then used normal .1uf on the rest? I think I could fit that
into two layers pretty easily.

-Mike
 
M

Mike Noone

Jan 1, 1970
0
nospam said:
Well the TDC-GPX is far from a 'standard' chip. Acam also strongly
recommend against using switchmode power supplies for it.

Unless you are prepared to do the development work to determine how
different decoupling schemes affect the chip performance I would take their
recommendations seriously. You could of course ask Acam for more
recommendations.

I asked the sales engineer for the US Acam distributor - and he didn't
seem to have a strong opinion on the matter. This was his response when
I asked him about the caps:

"The capacitors on Page 15 of the datasheet indicate that all the power
supply capacitors are 47 uF. This is quite a lot of capacitors, and
I'm sure it takes up a lot of space. Here are a couple of options.
First, if you have the space, you can layout the board so as to have
all the capacitors placed. Once you have a GPX prototype board
working, you can experiment by adding or subtracting capacitors to see
what effect it has. Also, you can experiment with different values or
different vendors as well. Second, if you don't have the space, you
can place as many capacitors as possible around the GPX. If the 1210
package size is too big, you could substitute 1206, 0805, or even 0603
packages."
I presume this isn't a cheap chip, the capacitors are not cheap, I don't
think I would trying to skimp on PCB layers to save a few bucks.

Nearly $200 in single quantities. I'm sure glad I'm not paying the
bill! :)
I also presume this is not your design and you are just doing PCB layout,
doesn't the designer have something to say about it?

It is my design, actually.

Thanks,

-Mike
 
J

J.A. Legris

Jan 1, 1970
0
Mike said:
Hi Joe - the precision of the TDC-GPX is necessary.

My question is whether or not they will improve things at all - if they
really are necessary. From what I know of decoupling, they will
decrease performance, not improve it. But like you said - it's not a
typical decoupling situation.

Thanks,

-Mike

Hi Mike,

Look at Fig. 9. The timing of the device is almost directly inversely
proportional to the power supply voltage - a power supply rejection
ratio of 1:1. If you want to maintain the timing precision to one part
in a million, you'll need a power supply with comparable precision. The
phase-locked loop and the LM317 can maintain this precision over the
long term, but over the very short term (where your measurements are
occurring), the control-loop is just coasting and the caps are doing
all the regulation.
 
J

John Popelish

Jan 1, 1970
0
Mike said:
Hi - I'm currently working on designing a board around the Acam TDC-GPX
time to digital converter chip. I've run into something which I found
to be incredibly odd. They reccomend 47uf caps on almost every single
vdd line. 12 in all. See page 54 (second to last page) of the datasheet
for the drawing I'm referring to:
http://www.acam.de/fileadmin/Download/pdf/English/DB_GPX_e.pdf

They reccomend use of Taiyo-Yuden LMK325BJ476MM, which is a 1210 47uf
cap available at digikey at the price of $34.10/10 caps. Thus for a
single board I would be using about $40 in just decoupling caps!!

Unless these chips draw huge and long current spikes, this
has to be over kill. For ordinary digital design, the
inductance of the caps and their connections is a lot more
important than the value of the capacitors.

If you can get one end of the capacitor right against the
chip pin, and use a pair of vias, one on each side of the
ground end of the capacitor, you should be able to get away
with much smaller caps. Oh, and avoid Z5U and Y5V
dielectrics. These pack so much capacitance into such small
metal area, that the resistance of the metal, itself can get
high enough to lower the effectiveness of the bypass.

You can get a Panasonic 0805 10 uF, 10 V X5R dielectric cap
for $0.79 each, from Digikey, and it is advertised to have
an ESR of .003 ohms. I doubt there is any advantage going
any larger than that, and considerably smaller would
probably be okay, also. If you can make a layout that takes
that, you can populate the first board with .1 uF or 1 uF
caps and if trouble shows up, increase the size up to 10 uF.
 
Mike said:
Hi - I'm currently working on designing a board around the Acam TDC-GPX
time to digital converter chip. I've run into something which I found
to be incredibly odd. They reccomend 47uf caps on almost every single
vdd line. 12 in all. See page 54 (second to last page) of the datasheet
for the drawing I'm referring to:
http://www.acam.de/fileadmin/Download/pdf/English/DB_GPX_e.pdf

They reccomend use of Taiyo-Yuden LMK325BJ476MM, which is a 1210 47uf
cap available at digikey at the price of $34.10/10 caps. Thus for a
single board I would be using about $40 in just decoupling caps!!

Typically, when I design a board, I put a .1uf 0603 ceramic on every
single supply pin of every IC, and then a single 10uf tantalum/ic on
the more sensitive ICs. My understanding was that this was more or less
the standard way to deal with decoupling.

So anyways - I'm starting to lay out this board - and these 12 1210s
are really getting in my way. They are making my life very difficult.
I'm trying to keep this as just a 2 layer board - but I'm not sure if I
can do it with all these damn 1210s all over the place.

My question is this: are such huge capacitors necessary? Are they even
worth it? The sales engineer for the distributor we purchased these
chips through didn't seem to have a good idea one way or the other. My
personal understanding was that it was better to have small but very
low esr caps on the supply pins, as opposed to really large capacity,
higher esr caps like these 1210s.

The only way to find out is to built the board and experiment.

Very high speed boards do demand rather more than the 0.1uF per device
and 10uF tantalum that you find on most boards.

Keep in mind that the 10uF tantalum probably works as damping resistors
rather than a capacitor - they tend to have pretty vile ESR's.

The Taiyo-Yuden parts seems to be a bit better than that.

http://www2.yuden.co.jp/hp/com/catalog/PDF_CATALOG/PDF/DJMK_E.PDF

If the data sheet calls for twelve 47uF parts from a specific supplier,
you are well advised to start off with that.

Keep in mind that application engineers aren't infallible - I once
slavishly copied an Analog Devices application circuit intended to
produce very stable reference voltage outputs, only to find that the
reference outputs oscillated - easy enough to fix with a couple of
extra components, but distinctly irritating. Happily, we needed a
second go-around on the layout for several other reasons ...
 
M

Mark

Jan 1, 1970
0
What does this chip do anyway...what is a time to digital converter?

Mark
 
N

nospam

Jan 1, 1970
0
J.A. Legris said:
Look at Fig. 9. The timing of the device is almost directly inversely
proportional to the power supply voltage - a power supply rejection
ratio of 1:1. If you want to maintain the timing precision to one part
in a million, you'll need a power supply with comparable precision.

I didn't look in detail at how the chip works but I'm sure it doesn't work
like that.

It has a 40MHz clock and I guess a chain of something like 300 81ps silicon
delay lines. On the 40MHz clock edge it can look at how many delay lines a
signal transition got through and so determine where within that 40MHz
clock cycle the signal transition occurred. That part of the precision
depends on the silicon delay and associated power supply sensitivity and is
about 1 part in 300, the rest of the precision comes from the 40MHz clock.

Also 47u capacitors are recommended on all the supply pins while only 2
supply pins carry the controlled delay line supply.

When you are trying to measure with 10's of ps resolution signals which
probably have 1000ps rise and fall times switching thresholds changing with
supply line noise would likely result in significant measurement jitter. I
suspect that is why they want to keep all the supplies as quiet as
possible.

Noise on the measured signals would be even worse which is why the OP
should be worried about everything else the measured signals touch on the
way to the chip not about skimping on capacitors and PCB layers (assuming
he really would like to get the precision the chip is theoretically capable
of).
--
 
D

DJ Delorie

Jan 1, 1970
0
Mike Noone said:
1. the software I use can only do two layers, unless I want to buy the
full version (currently using free version of Cadsoft's Eagle)

gEDA's PCB is free, and can do as many layers as you need, as big a
board as you need.
2. multilayer boards are quite expensive. I currently get my boards
through advanced pcb with their student $33 each special program - $33
+ shipping for a 2 layer board with 5 day turn around. I expect cost
for a 4 or 6 layer board would be at least a couple hundred dollars.

pcbpool can do single 4-layer boards for around a hundred bucks,
depending on size and turnaround time. You can omit the silkscreen to
save even more. A minimum-price 4 layer board (16 in2, no silk, 8
days) is $75.50 plus $10 S&H. They allow panels, too.

If you need more than one, pcbex can do five for around $160, again
depending on size and turnaround time.
 
J

J.A. Legris

Jan 1, 1970
0
nospam said:
I didn't look in detail at how the chip works but I'm sure it doesn't work
like that.

It has a 40MHz clock and I guess a chain of something like 300 81ps silicon
delay lines. On the 40MHz clock edge it can look at how many delay lines a
signal transition got through and so determine where within that 40MHz
clock cycle the signal transition occurred. That part of the precision
depends on the silicon delay and associated power supply sensitivity and is
about 1 part in 300, the rest of the precision comes from the 40MHz clock.

Also 47u capacitors are recommended on all the supply pins while only 2
supply pins carry the controlled delay line supply.

When you are trying to measure with 10's of ps resolution signals which
probably have 1000ps rise and fall times switching thresholds changing with
supply line noise would likely result in significant measurement jitter. I
suspect that is why they want to keep all the supplies as quiet as
possible.

Noise on the measured signals would be even worse which is why the OP
should be worried about everything else the measured signals touch on the
way to the chip not about skimping on capacitors and PCB layers (assuming
he really would like to get the precision the chip is theoretically capable
of).

Good points, but I think the PLL's controlled oscillator is used for
the time-base and it depends on a delay line too.
 
Top