47uf decoupling caps?!

[mkaras]

Problem with multilayer boards is two fold:
1. the software I use can only do two layers, unless I want to buy the
full version (currently using free version of Cadsoft's Eagle)
2. multilayer boards are quite expensive. I currently get my boards
through advanced pcb with their student $33 each special program - $33
+ shipping for a 2 layer board with 5 day turn around. I expect cost
for a 4 or 6 layer board would be at least a couple hundred dollars.

Oddly enough - I'm making two different things, both will use this
board:
1. A device that can measure the time between pulses on a single line.
The pulses come in on this line every couple nanoseconds to
microseconds. The pulses are about 20-50ns long as I recall. By
measuring the time between them this device will be generating,
apparently, pure random data. It will be an integral part of a ultra
high speed random number generator for use in quantum cryptography. I
don't understand any of the quantum stuff - I'm just an EE guy.
2. scanning laser rangefinder. We'll be using it to do time of flight
measurements on pulses being sent by a laser that is on a rotating
gimbal so that it can do 3D scans of an area.

So I'm wondering - I was told that the only really sensitive lines are
the VDDC lines. Maybe it would be OK if I just used these caps on those
lines, and then used normal .1uf on the rest? I think I could fit that
into two layers pretty easily.

-Mike

Mike Noone:
You would be well advised to make at least a four layer board for this
part. It is generally not possible to properly bypass the supply leads
to a device of the package type shown in the referenced data sheet if
you try to use a 2 layer board. Trust that myself and others that have
also suggested this to you really do know what we are talking about. By
the time you end up futzing through your third spin of a two layer
board trying to make it work you will have already spent the money it
would have taken to get the first pass on a four layer board.

- mkaras

 

[[email protected]]

I find this a very interesting post. A month or so ago I took a
workshop in high speed digital circuit design and learned a lot about
power supply decoupling. Basically everything you may think you know
is wrong. This guy is a consultant with more years than I have and
that is a lot. His experience has pretty much all been in doing high
speed circuit board design and everything he said was supported by an
explanation of the theory, simulation data and actual board test
results. So it is hard to argue with him.

He has data that shows that the rule of thumb of 0.1 uF cap per power
pin is way far over kill. In fact, the real high speed decoupling is
done by the power planes alone. The high speed noise can not be
smoothed by the caps simply because of their intrinsic inductance.
Further when they couple with the power plane capacitance, they really
do create a parallel resonance which *increases* the impedance at
certain frequencies.

His approach is to use closely spaced power and ground planes to create
a low impedance path at high frequencies. Then use a few 0.1 caps, a
few more 0.01 caps and a few more 0.001 caps. Of course the smaller
the package the better, but it is important to use parts that do not
have *too low* a value of ESR. The ESR will not affect the performance
of the caps, but it will minimize the peak of the parallel resonances
between all the different parts.

Er, I think the above paragraph needs further elaboration. ;-) I have
seen some sorry LDOs have problems with too low ESR, but geez, bypass
of a digital circuit having a problem with too low ESR?

 

[Rene Tschaggelar]

Oddly enough - I'm making two different things, both will use this
board:
1. A device that can measure the time between pulses on a single line.
The pulses come in on this line every couple nanoseconds to
microseconds. The pulses are about 20-50ns long as I recall. By
measuring the time between them this device will be generating,
apparently, pure random data. It will be an integral part of a ultra
high speed random number generator for use in quantum cryptography. I
don't understand any of the quantum stuff - I'm just an EE guy. [snip]

So I'm wondering - I was told that the only really sensitive lines are
the VDDC lines. Maybe it would be OK if I just used these caps on those
lines, and then used normal .1uf on the rest? I think I could fit that
into two layers pretty easily.

Mike,
if you want random data, then you can indeed save a lot
on the caps, just use 100nF. And also a 2layer board
is sufficient. Don't call it precision measurement.

Rene

 

[[email protected]]

What does this chip do anyway...what is a time to digital converter?

Detects pulses and produces a multi-bit digital output indicating the
length of the pulse.

The OP very sensibly posted a pointer to the datasheet for the part

http://www.acam.de/fileadmin/Download/pdf/English/DB_GPX_e.pdf

and you could usefully read that.

 

[Ian Bell]

OH, I should have looked at the datasheet first before typing.

You should have done that before you started designing.

Ian

 

[Ancient_Hacker]

Mike Noone wrote:

1. A device that can measure the time between pulses on a single line.
The pulses come in on this line every couple nanoseconds to
microseconds. The pulses are about 20-50ns long as I recall. By
measuring the time between them this device will be generating,
apparently, pure random data. It will be an integral part of a ultra
high speed random number generator for use in quantum cryptography.

You might consider a less speed-intensive way to get your random
numbers.
For instance you could measure two time intervals in a row and
concatenate the results.
For example if you want a 16-bit result, make two 8-bit measurements.
That way your clock only needs to be 1/256'th the resolution, so you
can use some cheap and common counters to do the job.

2. scanning laser rangefinder. We'll be using it to do time of flight
measurements on pulses being sent by a laser that is on a rotating
gimbal so that it can do 3D scans of an area.

This is usually done by modulating the laser and extracting the beat
frequency-- not by direct timing. It's a few bazillion times easier.


I know this isnt the answer you asked for, but you might want to
consider starting over with the design and use a bit more cleverness
and a bit less brute force. Do a little research and see how others
have handled similar measurement problems. Those kinds of things have
been done as far back as 1970, with 200MHz transistors, so we know it's
doable with relatively sedate parts.

Handling picosecond signals requires extreme care-- not something you
can do first-off with a 2-layer board. Look at PC motherboards-- they
have been having to use four or more layers since they went to 100MHz
bus speeds-- you're trying to handle signals 10 to 50 times as fast
with two layers. Just isnt going to happen.

Good luck,

 

[rickman]

Er, I think the above paragraph needs further elaboration. ;-) I have
seen some sorry LDOs have problems with too low ESR, but geez, bypass
of a digital circuit having a problem with too low ESR?

If you remember your basic AC circuits the paragraph should be self
explanatory. The problem is the parallel resonance which creates an
impedance peak. This can destroy the low impedance of a power
distribution system near the resonance frequency. If you remember that
the shape of a resonance is determined by the resistance in the circuit
which acts to damp resonance, you will realize that you need some
minimum level of ESR in the cap to lower the resonance peak. I have
not found any resources on the web to point you to which demonstrate
this, but the course I took with Lee Ritchey showed this in theory,
simulation and in real measurements.

It is important to remember that the ESR of a capacitor has little to
do with its decoupling ability. It sets the floor at self resonance,
but the remainder of the impedance-frequency plot is determined by the
capacitance and parasitic inductance.

Parallel resonance in power distribution systems is very real.

 

[rickman]

Problem with multilayer boards is two fold:
1. the software I use can only do two layers, unless I want to buy the
full version (currently using free version of Cadsoft's Eagle)
2. multilayer boards are quite expensive. I currently get my boards
through advanced pcb with their student $33 each special program - $33
+ shipping for a 2 layer board with 5 day turn around. I expect cost
for a 4 or 6 layer board would be at least a couple hundred dollars.

You can get free tools that support many layers. FreePCB seems to work
ok.
http://tech.groups.yahoo.com/group/FreePCB/

As to the cost, I think if you look around rather than assuming, you
will find any number of vendors who will provide low cost multilayer
PCBs.
http://www.pcbnet.com/
$50 for qty 1, 4 layers

Oddly enough - I'm making two different things, both will use this
board:
1. A device that can measure the time between pulses on a single line.
The pulses come in on this line every couple nanoseconds to
microseconds. The pulses are about 20-50ns long as I recall. By
measuring the time between them this device will be generating,
apparently, pure random data. It will be an integral part of a ultra
high speed random number generator for use in quantum cryptography. I
don't understand any of the quantum stuff - I'm just an EE guy.
2. scanning laser rangefinder. We'll be using it to do time of flight
measurements on pulses being sent by a laser that is on a rotating
gimbal so that it can do 3D scans of an area.

So I'm wondering - I was told that the only really sensitive lines are
the VDDC lines. Maybe it would be OK if I just used these caps on those
lines, and then used normal .1uf on the rest? I think I could fit that
into two layers pretty easily.

Like others have said, in general 2 layer boards are not a good idea
for sensitive circuits. It is possible to flood fill the signal layers
with power and ground to provide high frequency capacitance, but this
will not be as good as multilayer boards because the layers will be
spaced so far apart.

 

[[email protected]]

If you remember your basic AC circuits the paragraph should be self
explanatory. The problem is the parallel resonance which creates an
impedance peak. This can destroy the low impedance of a power
distribution system near the resonance frequency. If you remember that
the shape of a resonance is determined by the resistance in the circuit
which acts to damp resonance, you will realize that you need some
minimum level of ESR in the cap to lower the resonance peak. I have
not found any resources on the web to point you to which demonstrate
this, but the course I took with Lee Ritchey showed this in theory,
simulation and in real measurements.

It is important to remember that the ESR of a capacitor has little to
do with its decoupling ability. It sets the floor at self resonance,
but the remainder of the impedance-frequency plot is determined by the
capacitance and parasitic inductance.

Parallel resonance in power distribution systems is very real.

You need to think about what is the goal of decoupling. A chip has a
power surge. You want the local capacitance to provide the current for
this surge, rather than yank on a supply line that is really an
inductor in series with an ideal power source. The ability to prevent a
voltage drop at the IC is directly related to the ESR, and less is
more. ESR has everything to do with decoupling.

Granted it is not your theory that you are trying to defend, but it
lacks sound science.

 

[PeteS]

Why? ESL depends on case size, not capacitance.

John

Because smaller values typically come in smaller physical cases, of
course

Unless I am looking for a high voltage part, I can't easily find 0.01uF
in anything larger than 0805 (perhaps 0603) nowadays.

Cheers

PeteS

 

[Tom Bruhns]

If you remember your basic AC circuits the paragraph should be self
explanatory. The problem is the parallel resonance which creates an
impedance peak. This can destroy the low impedance of a power
distribution system near the resonance frequency. If you remember that
the shape of a resonance is determined by the resistance in the circuit
which acts to damp resonance, you will realize that you need some
minimum level of ESR in the cap to lower the resonance peak. I have
not found any resources on the web to point you to which demonstrate
this, but the course I took with Lee Ritchey showed this in theory,
simulation and in real measurements.

It is important to remember that the ESR of a capacitor has little to
do with its decoupling ability. It sets the floor at self resonance,
but the remainder of the impedance-frequency plot is determined by the
capacitance and parasitic inductance.

Parallel resonance in power distribution systems is very real.

Indeed. Somewhere recently I read a nice explanation of that, but it's
easy enough to simulate in Spice or RFSim99 or ... If you use two
widely-spaced capacitance values for bypassing, the impedance peak at a
frequency between their series resonances can be rather high. By using
values that are close enough together (such as your suggested 0.1, 0.01
and 0.001uF, or even more different values covering a similarly wide
range), you can control the maximum impedance over a fairly wide range
of frequencies. The close-spaced power-ground planes are great for the
really high frequencies, as you say. It's also helpful to put those
power and ground planes close to the surface where the parts to be
bypassed are. A via introduces 1/16 inch (1.6mm) of spacing between a
part on one side of the board and a plane on the opposite side. That
can be (almost certainly WILL be) a significant fraction of a
nanohenry, an impedance likely higher than the ESR at even 100MHz.

Note that for a given capacitance, you can lower the Q by either
LOWERING the inductance or RAISING the resistance. Lowering the
inductance has the added benefit of raising the resonant frequency,
allowing better bypassing at higher frequencies. Use parts with lowest
possible inductance; lay out the board with the lowest possible
additional inductance.

Back to the OP's question: I'd say a chip designed to require such
high bypass capacitance is a very poorly designed chip. In addition,
there is practically NO reason you should have to put that much
capacitance really close to the chip; power fed through an effectively
very low impedance transmission line from a low impedance power supply
at a distance will still look like a low impedance at the chip, even at
low frequencies.

Cheers,
Tom

 

[Uwe Bonnes]

....

Handling picosecond signals requires extreme care-- not something you
can do first-off with a 2-layer board. Look at PC motherboards-- they
...

The TDC is to measure with sub-nanosecond resolution, not to handle
sun-nanosecond signals. For sure, jitter of additional logic is a problem,
but the TDC is normally in the front of the signal chain.

Bye

 

[Tom Bruhns]

If you remember your basic AC circuits the paragraph should be self
explanatory. The problem is the parallel resonance which creates an
impedance peak. This can destroy the low impedance of a power
distribution system near the resonance frequency. If you remember that
the shape of a resonance is determined by the resistance in the circuit
which acts to damp resonance, you will realize that you need some
minimum level of ESR in the cap to lower the resonance peak. I have
not found any resources on the web to point you to which demonstrate
this, but the course I took with Lee Ritchey showed this in theory,
simulation and in real measurements.

It is important to remember that the ESR of a capacitor has little to
do with its decoupling ability. It sets the floor at self resonance,
but the remainder of the impedance-frequency plot is determined by the
capacitance and parasitic inductance.

Parallel resonance in power distribution systems is very real.

Further to this: a decent introduction to these concepts and bypassing
in general may be found in the PDF "white paper" at
http://www.avx.com/docs/techinfo/mlcbypas.pdf. I've seen similar
things from other capacitor manufacturers and from manufacturers of ICs
that depend on good bypassing (such as Xilinx).

It's not just theory. As rickman wrote, it's supported by practical
designs and measurements on those designs.

Cheers,
Tom

 

[John Larkin]

Because smaller values typically come in smaller physical cases, of
course

Unless I am looking for a high voltage part, I can't easily find 0.01uF
in anything larger than 0805 (perhaps 0603) nowadays.

Cheers

PeteS

Checking stock, we have

0603 2.2uF $0.08

0805 10uF $0.22

1206 22uF $1.04


The low-value caps cost 1-3 cents each.

John

 

[[email protected]]

Indeed. Somewhere recently I read a nice explanation of that, but it's
easy enough to simulate in Spice or RFSim99 or ... If you use two
widely-spaced capacitance values for bypassing, the impedance peak at a
frequency between their series resonances can be rather high. By using
values that are close enough together (such as your suggested 0.1, 0.01
and 0.001uF, or even more different values covering a similarly wide
range), you can control the maximum impedance over a fairly wide range
of frequencies.

What you are doing here makes sense. The smaller caps have less ESR and
ESL, so you are providing some bypass in frequency range where the
large caps have lost their edge due to ESR/ESL. Now granted it is not
much bypass since the cap is small, but it is better than nothing.

 

[DJ Delorie]

Checking stock, we have
0603 2.2uF $0.08
0805 10uF $0.22
1206 22uF $1.04

None of which are 0.01uF, so I don't understand what you're trying to
tell us.

A quick check of digikey shows that the lowest voltage rating of
0.01uF caps in 1206 or larger cases is 25 V. If you look at 01005
through 0805, the lowest voltage rating is 6.3 V (for 0201 and 01005
sizes). Although I'm not sure what that tells us, either.

 

[John Larkin]

None of which are 0.01uF, so I don't understand what you're trying to
tell us.

I'm telling you what we have in stock, and what they cost.

A quick check of digikey shows that the lowest voltage rating of
0.01uF caps in 1206 or larger cases is 25 V. If you look at 01005
through 0805, the lowest voltage rating is 6.3 V (for 0201 and 01005
sizes). Although I'm not sure what that tells us, either.

Couldn't agree more.

John

 

[John Larkin]

Further to this: a decent introduction to these concepts and bypassing
in general may be found in the PDF "white paper" at
http://www.avx.com/docs/techinfo/mlcbypas.pdf. I've seen similar
things from other capacitor manufacturers and from manufacturers of ICs
that depend on good bypassing (such as Xilinx).

This paper doesn't even mention plane impedance, which is the best way
to sell lots of capacitors, I guess.

John

 

[John Larkin]

Hi Joe - the precision of the TDC-GPX is necessary.

My question is whether or not they will improve things at all - if they
really are necessary. From what I know of decoupling, they will
decrease performance, not improve it. But like you said - it's not a
typical decoupling situation.

Thanks,

-Mike

What do these TDC chips cost?

John

 

[[email protected]]

Further to this: a decent introduction to these concepts and bypassing
in general may be found in the PDF "white paper" at
http://www.avx.com/docs/techinfo/mlcbypas.pdf. I've seen similar
things from other capacitor manufacturers and from manufacturers of ICs
that depend on good bypassing (such as Xilinx).

It's not just theory. As rickman wrote, it's supported by practical
designs and measurements on those designs.

Cheers,
Tom

The AVX paper doesn't agree:

High Q circuits make the troughs deeper and
peaks higher. To achieve a moderate Q circuit,
one must minimize ESL rather than increasing
the ESR, since it was already demonstrated that
ESR always creates a ripple voltage as shown in
Equation (12). Furthermore, reducing the ESL
will help avoid any unwanted resonances
between the board power plane capacitance and
the decoupling capacitor inductance.

See pages 7 and 8.