[snip]
This is a weird situation. Here's the history of how it got to this point.
The company I'm consulting for is developing a wireless chipset. They've
built a series of test chips over the last year to test various pieces of
their design, and my job is to do the board designs and some FPGA work. The
first test chip had 1.2V I/O. The Si4133 was already in the design when I
entered the picture, and I am not responsible for the RF parts of the
design. To get the 528MHz clock into the first test chip I used a very fast
diff-to-LVHSTL buffer from ICS that output a beautiful 1.2V single-ended
clock. But the rest of the 1.2V I/O (going to/from an FPGA) was a pain in
the ass.
On the next and two subsequent test chips the clock input became 3.3V
single-ended. I urged them to either go back to the 1.2V input or use a
differential input for the clock, but they've kept it at 3.3V. I'm not privy
to the reasons - I just have to make the boards work. I experimented with
some things on the last board that did not work out, so this time I want to
really solve the problem. I'm a digital guy and don't have a bag of analog
tricks to fall back on, but I've gotten some good ideas here that I'll look
into. Thanks to everyone who replied with suggestions.
Rob
Sounds like you are working for amateurs. Wireless chips, or chip
sets, don't use external clocks.
They use an external XTAL at (typically) 16MHz, and PLL the whole
she-bang.
Even on-chip, with no pin capacitances to drive, 500MHz is an upper
limit for CMOS. I usually use some form of PECL until I get down to
500MHz.