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74LVT transition times: How low can you go?

V

Vladimir Vassilevsky

Jan 1, 1970
0
Joerg said:
I could also do it with a 74HC14 but I wanted to avoid more chips.

RC and diode vs RC and 1G97. The diode is SOT-23 and so is 1G97. There
is no real difference.

VLV
 
J

Joerg

Jan 1, 1970
0
Vladimir said:
RC and diode vs RC and 1G97. The diode is SOT-23 and so is 1G97. There
is no real difference.

There is, however, a cost difference. A BAV70 runs you about a cent or
two. But in this app that wouldn't matter (it usually does in my apps
though).
 
J

Joerg

Jan 1, 1970
0
Jim said:
You could, (would cover more vendors), but to this Jim, using a part
with hysteresis IS 'doing it right'.
We've just designed in a Philips LVC2244 for that reason.

Yes, that one stated Schmitts. Wonder why they still have those
recommended tr/tf times in the data sheet. Oh well, I guess one can then
happily ignore those. Unfortunately only NXP mentions Schmitts, TI
doesn't unless I overlooked something. And NXP is out of stock :-(

To my mind, all logic should have hysteresis by default, but I
do note that the new universal gates 1G57/58/97/98 all have hystersis.
( and the better CPLDs now have it selectable by pin )

Agree, it all should. Would make life much easier.
 
J

Jim Granville

Jan 1, 1970
0
Joerg said:
Yes, that one stated Schmitts. Wonder why they still have those
recommended tr/tf times in the data sheet. Oh well, I guess one can then
happily ignore those.

See my earlier comment - they spec this so they can define the
tpd, and don't need to spend more time testing.
Unfortunately only NXP mentions Schmitts, TI
doesn't unless I overlooked something.

I just looked at IDT's offering, they spec :
VH Input Hysteresis VCC = 3.3V 100mV typ

And NXP is out of stock :-(

74LVC244A shows at Future and Digikey, in most packages ?

Today package of choice seems to be TSSOP20. Not as easy
to solder as SO20, but a whole heap smaller/thinner.

-jg
 
J

Joerg

Jan 1, 1970
0
Jim said:
See my earlier comment - they spec this so they can define the
tpd, and don't need to spend more time testing.



I just looked at IDT's offering, they spec :
VH Input Hysteresis VCC = 3.3V 100mV typ




74LVC244A shows at Future and Digikey, in most packages ?

Yes, indeed. I was looking at the one you had suggested further above,
the LVC2244 where there is no stock. Still, it's somewhat uncomfortable
to have to release only one manufacturer and ban others for the same
chip. But it sure ain't the first time.

Thanks again for the hint. The LVC244 (from NXP) looks like a good chip.

Today package of choice seems to be TSSOP20. Not as easy
to solder as SO20, but a whole heap smaller/thinner.

Yes, but I got used to it. Bought 3x glasses for lab work when TSSOP
came out ;-)

Meantime I became a bit careful if a chip is not migrated to TSSOP
because that could be an indicator that it's heading to lalaland.
 
J

Jim Granville

Jan 1, 1970
0
CBFalconer said:
Is that a CMOS package? If so, slow transition times will
seriously increase the power consumption, and (if excessive) can
actually destroy the chip. The reason is that at intermediate
levels both the pull-up and pull-down components are on, and are
fighting each other.


'Destroy the chip' sounds unlikely ?.
Yes, there is a dIcc/dVin peak, but the worst devices I've seen
have this at a few mA - so that's a few milliwatts.

More common is sub mA peaks, and the better devices have this peak
in the uA - like the CPLD we are using here, which has a peak
value of 80uA.
A schmitt Ip gives two peaks,in the Icc/Vin curve, and avoids
transistion oscillation.
-jg
 
J

John Larkin

Jan 1, 1970
0
Is that a CMOS package? If so, slow transition times will
seriously increase the power consumption, and (if excessive) can
actually destroy the chip. The reason is that at intermediate
levels both the pull-up and pull-down components are on, and are
fighting each other.

I think he's talking low duty cycles and fairly rapid slew through the
transition. I doubt the chip temperature would increase measurably.

I did recently post regarding a tiny logic triple buffer that was run
from +5 but driven from 3.3 volt logic. It was visibly hot on an ir
imager, +15c above ambient, with all three section inputs at +3.3. We
persuaded a single section to pull 45 mA by teasing the input voltage,
but it was probably oscillating too.

Never damaged one, though.

John
 
V

Vladimir Vassilevsky

Jan 1, 1970
0
John Larkin wrote:

I did recently post regarding a tiny logic triple buffer that was run
from +5 but driven from 3.3 volt logic. It was visibly hot on an ir
imager, +15c above ambient, with all three section inputs at +3.3. We
persuaded a single section to pull 45 mA by teasing the input voltage,
but it was probably oscillating too.

Never damaged one, though.

I did the same experiment with HCT04 gate powered from +5V. At 3.3V
input, it was draining 0.5mA. At 2V at the input, the current was 1mA.
The worst case consumption happened around 0.9V at the input, where it
was about 4mA.

I don't see any problems here.

Vladimir Vassilevsky

DSP and Mixed Signal Design Consultant

http://www.abvolt.com
 
R

rickman

Jan 1, 1970
0
I could also do it with a 74HC14 but I wanted to avoid more chips.


I might get away with 100nsec. There is going to be some intricate
address decoding, more than just a 688 and a 154.

To the OP, if you need 100 ns of delay to make your timing come out,
there may be a problem with the design. I am sure you know what you
are doing, but typically the /OE is used on all bus devices as the
timing control and the /CE is used for selection. Most devices
generate the /OE with enough timing margin relative to the address and
any CPU generated /CE controls that you shouldn't need to delay /OE.
You say your address decoding is very complex, is this what the /OE
delay is needed to compensate for? Is there a way to speed up the
address decode?

I would like to understand what the diode based circuit is doing. I
am primarily a digital designer and learned a long time ago that
analog components in a digital circuit usually meant someone was using
a bandaid or did not know how to do things "correctly". I'm not
saying this is a true statement, but this was the view I was taught.
Is the diode in series with the driver (with a resistor in parallel
with the diode) along with a pull up resistor and the cap? I would
like to see how this circuit would work just so I could use it if I
ever needed to. I think that (in opposition to my training) there are
times when a simple analog circuit is ok to use in a digital design,
for example, a clock detector using a differentiator and an RC
filter. But it is important to pay attention to voltage levels over
temperature to make sure enough voltage margin is preserved.
 
V

Vladimir Vassilevsky

Jan 1, 1970
0
rickman wrote:

I would like to understand what the diode based circuit is doing. I
am primarily a digital designer and learned a long time ago that
analog components in a digital circuit usually meant someone was using
a bandaid or did not know how to do things "correctly".

Good point. This is shamanism however it has to be done sometimes.
Remember the pull-up resistor on Z80 clock input? The modern CPUs have
the provision for picosecond timing adjustment on the signals.


I'm not
saying this is a true statement, but this was the view I was taught.
Is the diode in series with the driver (with a resistor in parallel
with the diode) along with a pull up resistor and the cap? I would
like to see how this circuit would work just so I could use it if I
ever needed to.

Diode in series with the resistor plus the other resistor in parallel.
Cap to the ground. The falling front is delayed, the raising front is
also delayed but for less amount of time.


I think that (in opposition to my training) there are
times when a simple analog circuit is ok to use in a digital design,
for example, a clock detector using a differentiator and an RC
filter. But it is important to pay attention to voltage levels over
temperature to make sure enough voltage margin is preserved.

As usual, it is nothing wrong the tricks like that as long as one
clearly knows what he is doing and what are the other implications.

Vladimir Vassilevsky

DSP and Mixed Signal Design Consultant

http://www.abvolt.com
 
R

rickman

Jan 1, 1970
0
Diode in series with the resistor plus the other resistor in parallel.
Cap to the ground. The falling front is delayed, the raising front is
also delayed but for less amount of time.

This is one of those circuits that may work ok and may not. The diode
drop will cause a noticable voltage drop. So the fast edge will rise/
fall to a point and then trail out to the "proper" voltage level.
Both edges will suffer from increased noise sensitivity due to the
slowed edge rate. This may or may not be an issue with your design
depending on the noise level. A schmitt trigger will deal with the
slowed signal edges much more effectively, but may be overkill for any
given app. I have not seen too many diodes that are significantly
smaller than one of the pico gates, so I don't use them for anything
other than ESD protection.
 
C

CBFalconer

Jan 1, 1970
0
rickman said:
.... snip ...

I would like to understand what the diode based circuit is doing. I
am primarily a digital designer and learned a long time ago that
analog components in a digital circuit usually meant someone was using
a bandaid or did not know how to do things "correctly". I'm not
saying this is a true statement, but this was the view I was taught.
Is the diode in series with the driver (with a resistor in parallel
with the diode) along with a pull up resistor and the cap? I would
like to see how this circuit would work just so I could use it if I
ever needed to. I think that (in opposition to my training) there are
times when a simple analog circuit is ok to use in a digital design,
for example, a clock detector using a differentiator and an RC
filter. But it is important to pay attention to voltage levels over
temperature to make sure enough voltage margin is preserved.

A diode into a RC pullup network can give a fast attack (for
negative transitions) and a controlled rise time (for positive
transitions). This assumes the driver can handle the negative
going current and that the receiver can stand the one diode drop
from ground level. Without the capacitor it can also be a
simple-minded level shifter.
 
J

Jim Granville

Jan 1, 1970
0
Vladimir said:
John Larkin wrote:



I did the same experiment with HCT04 gate powered from +5V. At 3.3V
input, it was draining 0.5mA. At 2V at the input, the current was 1mA.
The worst case consumption happened around 0.9V at the input, where it
was about 4mA.

I don't see any problems here.

From a power aspect, with HCT, you are correct.
With newer devices, that 4mA will go higher, but you'd still
struggle to kill a device.

The other issue that can bite, is transistion oscillation.
Without a Schmitt, if you scoped the output at the 4mA peak,
you will see what I mean.
That can cause real problems with downstream devices - I've seen
even unrelated pin drive have edge-oscillation effects that needed
external remedies.

-jg
 
J

Joerg

Jan 1, 1970
0
rickman said:
To the OP, if you need 100 ns of delay to make your timing come out,
there may be a problem with the design. I am sure you know what you
are doing, but typically the /OE is used on all bus devices as the
timing control and the /CE is used for selection. Most devices
generate the /OE with enough timing margin relative to the address and
any CPU generated /CE controls that you shouldn't need to delay /OE.
You say your address decoding is very complex, is this what the /OE
delay is needed to compensate for? Is there a way to speed up the
address decode?

Not really, unless I use a CPLD here which I don't want to. These board
should not contain any programmables. There are SPI devices and these
only have one enable, not /OE plus /CE. BTW they use various names for
that pin. Even within the same company (Analog Devices) it's called
/SYNC on the DACs I am using and /CS on the ADC.

On SPI the MISO line should be coming off tri-state a bit delayed to
make sure the others have definitely let go of it.

I would like to understand what the diode based circuit is doing. I
am primarily a digital designer and learned a long time ago that
analog components in a digital circuit usually meant someone was using
a bandaid or did not know how to do things "correctly". I'm not
saying this is a true statement, but this was the view I was taught.
Is the diode in series with the driver (with a resistor in parallel
with the diode) along with a pull up resistor and the cap? I would
like to see how this circuit would work just so I could use it if I
ever needed to. I think that (in opposition to my training) there are
times when a simple analog circuit is ok to use in a digital design,
for example, a clock detector using a differentiator and an RC
filter. But it is important to pay attention to voltage levels over
temperature to make sure enough voltage margin is preserved.

Cannot post a schematic from this computer but it's simple: Imagine an
RC with the R in series and a cap to ground. That creates a delay. Now
place a series combo of another R and a diode across the resistor and
the delay becomes shorter in one direction. That's basically it. When
you have Schmitts and fulfill the logic swing thresholds the diode is
ok. For really low voltage logic you can use a BAT54 but at 3.3V a
regular one is usually fine. I never shied away from combining analog
and logic. Built switcher supplies and what not around these.

Vladimir: I did not call shamans before releasing this stuff because I
am a Lutheran :)))
 
J

Jim Granville

Jan 1, 1970
0
Joerg wrote:
Not really, unless I use a CPLD here which I don't want to. These board
should not contain any programmables.

Care to elaborate why ?
There are SPI devices and these
only have one enable, not /OE plus /CE. BTW they use various names for
that pin. Even within the same company (Analog Devices) it's called
/SYNC on the DACs I am using and /CS on the ADC.

On SPI the MISO line should be coming off tri-state a bit delayed to
make sure the others have definitely let go of it.

In these situations (hand-over uncertainty), I've also seen simple
series resistors used. They keep the currents to safe levels, and
permit some latency tolerance, and normally the time frames are
short.

-jg
 
C

CBFalconer

Jan 1, 1970
0
Jim said:
.... snip ...

The other issue that can bite, is transistion oscillation.
Without a Schmitt, if you scoped the output at the 4mA peak,
you will see what I mean. That can cause real problems with
downstream devices - I've seen even unrelated pin drive have
edge-oscillation effects that needed external remedies.

Actually a Schmidt trigger input can make things worse. Without
it, a single CMOS inverter using a Vcc that allows a linear input
bias can stabilize using just a large resistor from output to
input. With it, the input voltage must be some sort of sawtooth,
depending on the innate input capacitance. The half period will be
the time needed for the input to rise (or fall) the hysteresis
voltage.
 
R

rickman

Jan 1, 1970
0
Not really, unless I use a CPLD here which I don't want to. These board
should not contain any programmables. There are SPI devices and these
only have one enable, not /OE plus /CE. BTW they use various names for
that pin. Even within the same company (Analog Devices) it's called
/SYNC on the DACs I am using and /CS on the ADC.

Now this is beginning to make some sense.

On SPI the MISO line should be coming off tri-state a bit delayed to
make sure the others have definitely let go of it.

Regardless of the name, all you need to do to prevent contention is
for the controller to delay enabling the next device for a period
after it disables the last device. Why is the controller not handing
this? That would be the "correct" digital approach to dealing with
this problem.

Cannot post a schematic from this computer but it's simple: Imagine an
RC with the R in series and a cap to ground. That creates a delay. Now
place a series combo of another R and a diode across the resistor and
the delay becomes shorter in one direction. That's basically it. When
you have Schmitts and fulfill the logic swing thresholds the diode is
ok. For really low voltage logic you can use a BAT54 but at 3.3V a
regular one is usually fine. I never shied away from combining analog
and logic. Built switcher supplies and what not around these.

The reason to be careful combining digital and analog in these ways is
because of how the digital thresholds vary over temperature, voltage
and process. You can model, test and analyze, but you still need to
allow plenty of margin for things you don't easily control such as
process variation and noise.

Heck, I saw a circuit that simply used a FET to control the current
through an LED. But the transfer characteristics of the FET are not
well controlled. After two years of use in a design they tweeked
their process and the circuit stopped working due to the rise in
threshold voltage. Not a lot, just enough to make the LEDs too dim to
really see.
 
J

John Larkin

Jan 1, 1970
0
Not really, unless I use a CPLD here which I don't want to. These board
should not contain any programmables. There are SPI devices and these
only have one enable, not /OE plus /CE. BTW they use various names for
that pin. Even within the same company (Analog Devices) it's called
/SYNC on the DACs I am using and /CS on the ADC.

On SPI the MISO line should be coming off tri-state a bit delayed to
make sure the others have definitely let go of it.


Why bother? A little transient bus contention never hurt anybody.

John
 
V

Vladimir Vassilevsky

Jan 1, 1970
0
rickman wrote:

Heck, I saw a circuit that simply used a FET to control the current
through an LED.

Great. I have seen bunch of leds connected in parallel. Another good one
is driving a led by logic '1' directly from a chip. But the best
solution I ever heard of is using comparator as opamp in the measurement
circuit! And after that somebody complains about the software...

Vladimir Vassilevsky

DSP and Mixed Signal Design Consultant

http://www.abvolt.com
 
V

Vladimir Vassilevsky

Jan 1, 1970
0
Joerg wrote:

Cannot post a schematic from this computer but it's simple: Imagine an
RC with the R in series and a cap to ground. That creates a delay.
Vladimir: I did not call shamans before releasing this stuff because I
am a Lutheran :)))

I see. You want to be more holy than a Pope, Larkin and Rickman
altogether, that is what this circuit for :)))

VLV
 
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