V
Vladimir Vassilevsky
- Jan 1, 1970
- 0
Joerg said:I could also do it with a 74HC14 but I wanted to avoid more chips.
RC and diode vs RC and 1G97. The diode is SOT-23 and so is 1G97. There
is no real difference.
VLV
Joerg said:I could also do it with a 74HC14 but I wanted to avoid more chips.
Vladimir said:RC and diode vs RC and 1G97. The diode is SOT-23 and so is 1G97. There
is no real difference.
Jim said:You could, (would cover more vendors), but to this Jim, using a part
with hysteresis IS 'doing it right'.
We've just designed in a Philips LVC2244 for that reason.
To my mind, all logic should have hysteresis by default, but I
do note that the new universal gates 1G57/58/97/98 all have hystersis.
( and the better CPLDs now have it selectable by pin )
Joerg said:Yes, that one stated Schmitts. Wonder why they still have those
recommended tr/tf times in the data sheet. Oh well, I guess one can then
happily ignore those.
Unfortunately only NXP mentions Schmitts, TI
doesn't unless I overlooked something.
And NXP is out of stock :-(
Jim said:See my earlier comment - they spec this so they can define the
tpd, and don't need to spend more time testing.
I just looked at IDT's offering, they spec :
VH Input Hysteresis VCC = 3.3V 100mV typ
74LVC244A shows at Future and Digikey, in most packages ?
Today package of choice seems to be TSSOP20. Not as easy
to solder as SO20, but a whole heap smaller/thinner.
CBFalconer said:Is that a CMOS package? If so, slow transition times will
seriously increase the power consumption, and (if excessive) can
actually destroy the chip. The reason is that at intermediate
levels both the pull-up and pull-down components are on, and are
fighting each other.
Is that a CMOS package? If so, slow transition times will
seriously increase the power consumption, and (if excessive) can
actually destroy the chip. The reason is that at intermediate
levels both the pull-up and pull-down components are on, and are
fighting each other.
I did recently post regarding a tiny logic triple buffer that was run
from +5 but driven from 3.3 volt logic. It was visibly hot on an ir
imager, +15c above ambient, with all three section inputs at +3.3. We
persuaded a single section to pull 45 mA by teasing the input voltage,
but it was probably oscillating too.
Never damaged one, though.
I could also do it with a 74HC14 but I wanted to avoid more chips.
I might get away with 100nsec. There is going to be some intricate
address decoding, more than just a 688 and a 154.
I would like to understand what the diode based circuit is doing. I
am primarily a digital designer and learned a long time ago that
analog components in a digital circuit usually meant someone was using
a bandaid or did not know how to do things "correctly".
saying this is a true statement, but this was the view I was taught.
Is the diode in series with the driver (with a resistor in parallel
with the diode) along with a pull up resistor and the cap? I would
like to see how this circuit would work just so I could use it if I
ever needed to.
times when a simple analog circuit is ok to use in a digital design,
for example, a clock detector using a differentiator and an RC
filter. But it is important to pay attention to voltage levels over
temperature to make sure enough voltage margin is preserved.
Diode in series with the resistor plus the other resistor in parallel.
Cap to the ground. The falling front is delayed, the raising front is
also delayed but for less amount of time.
rickman said:.... snip ...
I would like to understand what the diode based circuit is doing. I
am primarily a digital designer and learned a long time ago that
analog components in a digital circuit usually meant someone was using
a bandaid or did not know how to do things "correctly". I'm not
saying this is a true statement, but this was the view I was taught.
Is the diode in series with the driver (with a resistor in parallel
with the diode) along with a pull up resistor and the cap? I would
like to see how this circuit would work just so I could use it if I
ever needed to. I think that (in opposition to my training) there are
times when a simple analog circuit is ok to use in a digital design,
for example, a clock detector using a differentiator and an RC
filter. But it is important to pay attention to voltage levels over
temperature to make sure enough voltage margin is preserved.
Vladimir said:John Larkin wrote:
I did the same experiment with HCT04 gate powered from +5V. At 3.3V
input, it was draining 0.5mA. At 2V at the input, the current was 1mA.
The worst case consumption happened around 0.9V at the input, where it
was about 4mA.
I don't see any problems here.
rickman said:To the OP, if you need 100 ns of delay to make your timing come out,
there may be a problem with the design. I am sure you know what you
are doing, but typically the /OE is used on all bus devices as the
timing control and the /CE is used for selection. Most devices
generate the /OE with enough timing margin relative to the address and
any CPU generated /CE controls that you shouldn't need to delay /OE.
You say your address decoding is very complex, is this what the /OE
delay is needed to compensate for? Is there a way to speed up the
address decode?
I would like to understand what the diode based circuit is doing. I
am primarily a digital designer and learned a long time ago that
analog components in a digital circuit usually meant someone was using
a bandaid or did not know how to do things "correctly". I'm not
saying this is a true statement, but this was the view I was taught.
Is the diode in series with the driver (with a resistor in parallel
with the diode) along with a pull up resistor and the cap? I would
like to see how this circuit would work just so I could use it if I
ever needed to. I think that (in opposition to my training) there are
times when a simple analog circuit is ok to use in a digital design,
for example, a clock detector using a differentiator and an RC
filter. But it is important to pay attention to voltage levels over
temperature to make sure enough voltage margin is preserved.
Not really, unless I use a CPLD here which I don't want to. These board
should not contain any programmables.
There are SPI devices and these
only have one enable, not /OE plus /CE. BTW they use various names for
that pin. Even within the same company (Analog Devices) it's called
/SYNC on the DACs I am using and /CS on the ADC.
On SPI the MISO line should be coming off tri-state a bit delayed to
make sure the others have definitely let go of it.
Jim said:.... snip ...
The other issue that can bite, is transistion oscillation.
Without a Schmitt, if you scoped the output at the 4mA peak,
you will see what I mean. That can cause real problems with
downstream devices - I've seen even unrelated pin drive have
edge-oscillation effects that needed external remedies.
Not really, unless I use a CPLD here which I don't want to. These board
should not contain any programmables. There are SPI devices and these
only have one enable, not /OE plus /CE. BTW they use various names for
that pin. Even within the same company (Analog Devices) it's called
/SYNC on the DACs I am using and /CS on the ADC.
On SPI the MISO line should be coming off tri-state a bit delayed to
make sure the others have definitely let go of it.
Cannot post a schematic from this computer but it's simple: Imagine an
RC with the R in series and a cap to ground. That creates a delay. Now
place a series combo of another R and a diode across the resistor and
the delay becomes shorter in one direction. That's basically it. When
you have Schmitts and fulfill the logic swing thresholds the diode is
ok. For really low voltage logic you can use a BAT54 but at 3.3V a
regular one is usually fine. I never shied away from combining analog
and logic. Built switcher supplies and what not around these.
Not really, unless I use a CPLD here which I don't want to. These board
should not contain any programmables. There are SPI devices and these
only have one enable, not /OE plus /CE. BTW they use various names for
that pin. Even within the same company (Analog Devices) it's called
/SYNC on the DACs I am using and /CS on the ADC.
On SPI the MISO line should be coming off tri-state a bit delayed to
make sure the others have definitely let go of it.
Heck, I saw a circuit that simply used a FET to control the current
through an LED.
Cannot post a schematic from this computer but it's simple: Imagine an
RC with the R in series and a cap to ground. That creates a delay.
Vladimir: I did not call shamans before releasing this stuff because I
am a Lutheran ))