S

#### Sean McIlroy

- Jan 1, 1970

- 0

this will be my first attempt at formulating a sensible question about

this stuff. you've been warned. here's the question...

unless i've already misinterpreted something (http://

webpages.ursinus.edu/lriley/ref/circuits/img96.gif) the following is

an NPN transistor NOT gate:

================================================================

-- V[B1] -- << R

**>> -- V[B1] -- << base >>**

-- V[C1] -- << R[C] >> -- V[C1] -- << collector >>

<< ground >> --------------------- << emitter >>

================================================================

hence one has

V[C2]

= V[C1] - R[C] * I[C]

= V[C1] - R[C] * I

-- V[C1] -- << R[C] >> -- V[C1] -- << collector >>

<< ground >> --------------------- << emitter >>

================================================================

hence one has

V[C2]

= V[C1] - R[C] * I[C]

= V[C1] - R[C] * I

*** gain**

= V[C1] - ( gain * R[C] / R= V[C1] - ( gain * R[C] / R

**) * ( V[B1] - V[B2] )**

but the webpage (http://webpages.ursinus.edu/lriley/ref/circuits/

node4.html) seems to be saying that there are m,b (m<0) with

V[C2] = m * V[B1] + b

perhaps V[B2] is fixed for reasons unknown to me?

peace

stmbut the webpage (http://webpages.ursinus.edu/lriley/ref/circuits/

node4.html) seems to be saying that there are m,b (m<0) with

V[C2] = m * V[B1] + b

perhaps V[B2] is fixed for reasons unknown to me?

peace

stm