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AC to ADC design question

NiGHTS

Nov 19, 2014
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I am trying to build a simple interface circuit where a signal input of about 30VAC can be converted to a range that can be safely processed by an MCU's ADC input pin. Here is a sketch of a schematic I came up with that might perform this conversion, but I'm not sure if it will work. I built something similar in a solderless breadboard but the op-amps I was using didn't seem to be producing the output I was expecting (TLV2782IP). I have a feeling I'm not using the appropriate op-amp. Either way, I'd love some feedback to know if maybe I'm approaching this incorrectly, and if so how. Thanks!
ac-to-adc.png
 

NiGHTS

Nov 19, 2014
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Hello,

An opamp that has no negative powersupply can not have a negative output.
Have a look at this circuit from the AAC eBook...

Bertus
This doesn't seem to work either. And to simplify this even more as a debugging strategy, I tried removing the op-amp just to see if the inputs produce an addition of any kind. It does not...

1690832013558.png
I've also tried this in a simple circuit simulator with and without an op-amp, using that specific configuration. There appears to be no noticeable voltage addition from the inputs of this "summer circuit". Could the author be lying? Has anyone ever actually tried doing this before?

Any thoughts? Thanks again for your help!
---

EDIT: I have some thoughts on what I am doing wrong. I think I am supposed to power the op-amp with +3.3V high, -3.3V low instead of +3.3V high, 0V low. That way it would pull current away from the inputs to create a solution with the polarity flipped around. Am I on the right track here?
 
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Delta Prime

Jul 29, 2020
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I tried removing the op-amp just to see if the inputs produce an addition of any kind. It does not...

1690832013558.png

I've
You have just proven that it does not do addition What you have there is a passive averaging circuit if you were to add an additional resistor (& identical voltage source), with a different value you will see the voltage drops across these resistors would be different ,they would average.
Operational amplifiers;
voltage adder,
Summing amplifier,
summing inverter.
Are the same thing.
Vout of op amp is the sum of the inputs and is proportional to the voltage drops across the resistors.
Connected to the inverting input of the amplifier.
 
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Harald Kapp

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You have just proven that it does not do addition What you have there is a passive averaging circuit
Averaging is addition followed by division by the number of elements. Exactly what is stated in post #2.
There appears to be no noticeable voltage addition from the inputs of this "summer circuit".
As above: the output is [math]\frac{1.5 V + 1.5 V}{2} = 1.5 V[/math]This is why the circuit in post #3 uses a gain of 3 in the opamp circuit to compensate for the division.

Here's a completely passive circuit incl. simulation:
1690871362120.png
The green waveform shows V(in), a sine with 50 Hz, 40 V amplitude.
The blue waveform shows the output: a 1.75 V DC offset superimposed with the scaled down input voltage such that the output is a sine with 50 Hz, between 0 V and 3.3 V.

Note that when you want to use opamps in a single supply scheme, you may have to use rail-to-rail opamps. Other wise yo may observe clipping of the output near 0 V and VCC
 

Delta Prime

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Averaging is addition followed by division by the number of elements. Exactly what is stated in post #2

Based on what I have read of his understanding I would be able to explain it in a way that makes sense to a layman I wouldn't presume to advise you correctly on the problem the TS is having he's clearly looking for the resulting voltage values that are greater than the combined voltages it would have become clear to the TS if he or she would have responded before your insight on Ohm's law. As stated before....I know the constants. The TS was the only variable. Two steps ahead!
You have just proven that it is not.
 

Hermano

Aug 1, 2023
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This circuit may help:
1690891776747.png
1690891834540.png
If you use Rg=10k and Rf=1k, it will divide input voltage by 10 and will reference it to Vref.
Here is its simulation results for input AC voltage with amplitude 10V and Vref=2.5V:
1690892217030.png
1690892112465.png
 

NiGHTS

Nov 19, 2014
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This circuit may help:
View attachment 60124
View attachment 60125
If you use Rg=10k and Rf=1k, it will divide input voltage by 10 and will reference it to Vref.
Here is its simulation results for input AC voltage with amplitude 10V and Vref=2.5V:
View attachment 60127
View attachment 60126
¡Estoy muy agradecido, mi hermano!

I think I'm becoming more clear on the concepts, so here is my latest circuit which at least according to a simple simulator seems to do the trick.

Now for my rationale. Your vref circuit is very useful, and certainly works as intended without the need for a negative rail. Unfortunately, at the voltage I am interested in accepting, the vref would have to be too high for the math to work out. So I've remixed some concepts I've learned here. First I drop the voltage using a simple voltage divider. If I tied this directly to your VIN input, that would introduce a resistor network that skews the voltage at the inverting input of the op-amp. So to ensure that the new divided voltage is driven, I introduced an AC buffer, but this configuration requires a negative rail, which means I'll use an LDO VReg that can pump out a negative voltage. Since now the rail-to-rail is double wide, I divide it in half in the zero-line shifter.

I still need to verify it with real-world parts to confirm. Any objections with my circuit update?

1690904843138.png

Thank you again for all your help guys!

(P.S. you have an error in your simulation schematic. R3 should be Rg and R4 should be Rf)
 

NiGHTS

Nov 19, 2014
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You can, yes, as well as eliminate the initial voltage divider, but the vref would need to be 30V in my case, as far as I understand it. And if that's the case, I'd be better off using two op-amps because it would be cheaper to use a second op-amp gate and a tiny reference-level negative voltage than regulate such a large constant voltage in my application. Correct me if I'm wrong.
 

Hermano

Aug 1, 2023
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Additional divider is not needed: the circuit can have Gain <1 and you can tune it to anything you need. In my example I used 1:10, you can set it to 1:100 - no need for additional divider.
You also don't need to change Vref: it still will stay 2.5V. Why I used 2.5V? Because I assumed the rail is 5V, so middle point is 2.5V and it is not changing if you change the gain.
As for the mistake you pointed out: there is a chance the mistake is in the TI article (I didn't notice until you mentioned the difference). To check that just short the Vin to GND (middle voltage of your AC voltage) and Vout needs to be equal to Vref (2.5V). To achieve that you'll notice that Rf and Rg need to be swapped over (as it is in my simulation).
Here is simulation to have 100VAC (peak-to-peak, around 70VAC RMS):
1690969706745.png
1690969895344.png
I hope this helps.
 

danadak

Feb 19, 2021
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Some times one cannot see the forest for the trees blocking the view.....:)
 

NiGHTS

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Additional divider is not needed: the circuit can have Gain <1 and you can tune it to anything you need. In my example I used 1:10, you can set it to 1:100 - no need for additional divider.
You also don't need to change Vref: it still will stay 2.5V. Why I used 2.5V? Because I assumed the rail is 5V, so middle point is 2.5V and it is not changing if you change the gain.
As for the mistake you pointed out: there is a chance the mistake is in the TI article (I didn't notice until you mentioned the difference). To check that just short the Vin to GND (middle voltage of your AC voltage) and Vout needs to be equal to Vref (2.5V). To achieve that you'll notice that Rf and Rg need to be swapped over (as it is in my simulation).
Here is simulation to have 100VAC (peak-to-peak, around 70VAC RMS):
View attachment 60142
View attachment 60144
I hope this helps.
Alright, I see it now. Actually, my math was wrong partly from that confusion with the schematic inconsistency. But looking more carefully at the documents mentioned in this thread showed me what I was doing wrong. So I've finally arrived to the solution:
1690993766028.png
This worked correctly in both simulation and on a solderless breadboard. Again, thank you all for your help! This was very educational.
 

danadak

Feb 19, 2021
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Sim of your new design :

1691016313414.png

Circuit with correct Vref :

1691015528480.png

Regards, Dana.
 
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NiGHTS

Nov 19, 2014
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Sim of your new design :

View attachment 60162

Circuit with correct Vref :

View attachment 60161

Regards, Dana.

Dana,

I appreciate that you took the extra time to double-check my design. Unfortunately you seem to have made a mistake reproducing it and then offered an inferior alternative to my most recent proposal.

To be more specific, the simulation you claim to be of my design has an arbitrary 1.6V reference voltage before the divider. Mine is sourced by a 3.3V source, divided so that the positive input of the op-amp becomes 1.563V. In your interpretation of my schematic, the positive input would become 0.758V. This is a critical flaw as it would cause the resulting waveform to be about 0.8V lower than it should be, as evidenced in your plot.

Your suggestion is also flawed. The requirement was to produce an output where the peak output voltage is 3.3V and the lowest is 0V. It seems your plot only makes it up to about 1.9V with the lowest at 1.3V. In addition, your schematic requires a 1.6V driven reference, thus it implies that more support circuitry is needed to implement your suggestion.

My schematic eliminates the requirement of a driven reference voltage by making use of the op amp power supply. And despite the resistor values being an approximation, the output voltage is at lowest 930µV and highest at 3.299V with no clipping.

1691076168079.png

Either way, again I appreciate your effort and thank you for your time!
 
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danadak

Feb 19, 2021
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I most certainly did screw up that sim. I was plodding away thinking I want a 1.6 V Vref,
thinking Vdd was 3.2, and promptly labeled that source in sim as 1.6, not the correct value
for the input to the divider. Or the correct Vdd....

I made the changes to your design and get some odd results :

1691094410341.png

First of all I get a peak of 3.26928 and min of 11.517 mV. My thought is take an RRIO opamp
and load it with a fdbk network and it is no longer "true" RRIO.

Second this is a RRO only opamp and the crazy 6 or so uV differential transitions at input (I ran sim at 1 uV
accuracy) seems out of place. And as you can see the width of the transition, for positive peak results in
a flattening of Vout. Guessing this is load related issue of some kind. Or internal bias supply for the output
driver....? Note ADI Spice model was used for this.

1691093926248.png



Lastly if accuracy is concerned one would use a Vref part to supply the 3.3V needed for OpAmp power and circuit
Vref, so that error is removed. Eg Vref for circuit derived from a main and noisey supply V which our circuits using.
Not a good idea unless 6 - 7 bit absolute accuracy all that is needed. Of course that error would be added to A/D
internal Vref in doing total error analysis. Maybe his processor is Vref derived ratiometric to supply..... a R divider
off its Vdd ?

Note we both used 3.3V as supply V, but all the specs in ADI datasheet wrapped around 5V or greater. That may
be the cause of my sim .....


Regards, Dana.
 
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NiGHTS

Nov 19, 2014
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I most certainly did screw up that sim. I was plodding away thinking I want a 1.6 V Vref,
thinking Vdd was 3.2, and promptly labeled that source in sim as 1.6, not the correct value
for the input to the divider. Or the correct Vdd....

I made the changes to your design and get some odd results :

View attachment 60171

First of all I get a peak of 3.26928 and min of 11.517 mV. My thought is take an RRIO opamp
and load it with a fdbk network and it is no longer "true" RRIO.

Second this is a RRO only opamp and the crazy 6 or so uV differential transitions at input (I ran sim at 1 uV
accuracy) seems out of place. And as you can see the width of the transition, for positive peak results in
a flattening of Vout. Guessing this is load related issue of some kind. Or internal bias supply for the output
driver....? Note ADI Spice model was used for this.

View attachment 60170



Lastly if accuracy is concerned one would use a Vref part to supply the 3.3V needed for OpAmp power and circuit
Vref, so that error is removed. Eg Vref for circuit derived from a main and noisey supply V which our circuits using.
Not a good idea unless 6 - 7 bit absolute accuracy all that is needed. Of course that error would be added to A/D
internal Vref in doing total error analysis. Maybe his processor is Vref derived ratiometric to supply..... a R divider
off its Vdd ?

Note we both used 3.3V as supply V, but all the specs in ADI datasheet wrapped around 5V or greater. That may
be the cause of my sim .....


Regards, Dana.
I think what you are trying to convey to me is that if I don't use a driven reference on the non-inverting input, the op-amp input bias current that occurs when the inverting input switches it's polarity could in turn cause the simple voltage divider at the non-inverting input to momentarily corrupt the 1.563V reference and making the output voltage somewhat inaccurate at the peaks.

As for why the change in polarity of the inverting input might contribute to a change in the impedance of the non-inverting input, maybe it has something to do with the common mode rejection ratio, or some kind of parasitic capacitance in the internal transistor gates that fight against a polarity change momentarily.

Either way, I'm glad you pointed this out. In the application I plan on using this circuit inaccuracy like this is inconsequential, but I can see this being a problem with high frequency AC signals, and perhaps an op-amp with tighter tolerances can deal with this better.

Thanks again!
 
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