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Three logic inverters in a series loop is a naturally unstable configuration that will oscillate at the highest frequency the gate propagation delay will allow. This circuit inserts an RC low-pass filter in the loop to increase one of the gate delays and reduce the loop oscillation frequency. Note that all nodes in this circuit are at hard logic levels except for the input to U4. It appears that the capacitor makes use of the unseen input protection diodes on U4 for part of its discharge cycle. Also, if the capacitor is electrolytic then I would look more closely at polarity over a full cycle because it seems to be charged in a bipolar fashion.
There are many different types of oscillators.
This one is presumably designed to use CMOS inverters.
This can be broken down into two main groups. Those with an even number of inverters, and those with an odd number.
If you consider the case of an odd number -- your case -- then you can sort of model it as a 1 bit chasing itself around the loop. As laplace suggests, this is unstable (it will always oscillate) and the purpose of the RC element is to slow it down.
There is also an oscillator with an even number of gates (usually 2) which is often seen. The problem with this is that it is actually stable in one of 2 states, and poor design may mean that it won't oscillate at all.
National Semiconductor has an excellent application note which discusses oscillators, and from which you can get a heap of useful information.
You might wonder why your oscillator has three gates, when 2 in series appear to do nothing. The reason is that the model of it chasing a 1 around is not actually correct. CMOS inverters act as very high gain amplifiers, and CAN be biased to operate in their (very small) linear region. If you tried this with only a single inverter, it would be unreliable.
However, if you replaced the inverters with Schmitt trigger inverters, you can make a 1 gate oscillator which is well behaved. This is due to the fact that the gate has no linear region, and instead has hysteresis which makes it able to operate it very much like a 2 terminal 555
This one is presumably designed to use CMOS inverters.
This can be broken down into two main groups. Those with an even number of inverters, and those with an odd number.
If you consider the case of an odd number -- your case -- then you can sort of model it as a 1 bit chasing itself around the loop. As laplace suggests, this is unstable (it will always oscillate) and the purpose of the RC element is to slow it down.
There is also an oscillator with an even number of gates (usually 2) which is often seen. The problem with this is that it is actually stable in one of 2 states, and poor design may mean that it won't oscillate at all.
National Semiconductor has an excellent application note which discusses oscillators, and from which you can get a heap of useful information.
You might wonder why your oscillator has three gates, when 2 in series appear to do nothing. The reason is that the model of it chasing a 1 around is not actually correct. CMOS inverters act as very high gain amplifiers, and CAN be biased to operate in their (very small) linear region. If you tried this with only a single inverter, it would be unreliable.
However, if you replaced the inverters with Schmitt trigger inverters, you can make a 1 gate oscillator which is well behaved. This is due to the fact that the gate has no linear region, and instead has hysteresis which makes it able to operate it very much like a 2 terminal 555
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