- Jan 1, 1970
Terry said:Hi Joerg,
almost all of my SMPS are Peak Current-Mode Controlled - that being
said, the ones I am doing now are voltage-mode controlled, but with peak
we are talking about the same thing, but I shall elucidate.
at FET turn-on, the gate current flows the current sense resistor Rs,
causing a spike. for low-power converters that switch quickly, this
spike can be large - possibly even troublesome. I often re-route the
gatedrive current away from Rs to avoid this.
and also when the FET turns on, it has to charge the xfmr/snubber/etc
capacitance. this Cx*dV/dt current also flows thru Rs, again causing
problems. not many cute tricks to get rid of this - but in DCM can turn
on nice and slow (ware start-up though, it wont be DCM). of course the
FET Cds doesnt cause trouble, other than heating up the FET.
making a very efficient low power PCMC supply that runs from high
voltage can thus be a real PITA - low power = large Rs; high efficiency
generally means fast FET switching hence high CdV/dt current into Rs
I found that a nice ceramic cap across Rsense takes care if this quite
well. Large enough to muffle the spike but small enough not to skew the
ramp too much. After all, it's only used to detect when a desired
cut-off has been reached.
Many of my designs have to go from full bore all the way down to zero
output current, and sometimes also zero volts meaning it has to be a
forward converter or SEPIC. Never been a problem really. Below a certain
load they go into "pulse rate stretch" or in modern SMPS lingo pulse
skipping, although technically stretching has nothing to do with skipping.