BJTs used as spdt

[bredniol]

Hello everyone
I have found this circuit on the net


When the switch is closed the first led led is on, the second is off.
When the switch is open the first led is off, the second is on.

1. I'm ok with the biasing for the first bjt, but not sure with the second.
When the switch is open it Q2 is into saturation (Q1 in cutoff) and that's ok.
But, why when the switch is closed Q2 goes into cutoff?

2. Whould it be possible to get the same results using npn and the switch opening/closing to V+?

Thanks

 

[danadak]

Because Q1, if in sat, pulls up the first diode so the V at junction of
first diode cathode is ~ 5 - { .7 (diode) + .2 (Vsat) } =~ 4.1V. That
is not low enough to get Q2 and its base diode turned on, turned
on hard. You would need the second diode and Vbe Q2 turned
on which is ~ .7 + .7 =~ 1.4V.

This also works (depending on LED current you want) :



Note you might also add a R from base to ground, say 10K, to absorb leakage
when inoput is grounded, to keep Q1 from turning on. LEDs these daya can glow
with uA of current, so need to make sure Q1 fully off.

https://tinyurl.com/2khoc799

Click on switch


Regards, Dana.

 

[AnalogKid]

1. Yes, it is possible with two NPN transistors; or with one NPN and one PNP.

2. The components do not have reference designators, so I'll assume that you mean that Q1 is the one on the left.

3. There are indeed problems with Q2. Among other things, you must eliminate D1 and can eliminate D2.

And as above, you can eliminate one transistor if it is acceptable to have one full LED current sourced by a GPIO pin. I would do it differently, not running the full LED current through a small signal transistor base.

More later.

ak

 

[bredniol]

Thanks both!

Actually I'll need this for a circuit that doesn't have GPIO.
It's a power supply, V+ is 15V (24V in another version of it), I have swtiched barrel jack as output and I want to use that switch to drive a bicolor led. So, when nothing is connected to the power supply the led is red, but when something is connected the led turns blue.

 

[danadak]

AnalogKids point about running LED current thru base good caution.

Looking at a 2N3904, assuming your current is in range of 100 mA or
less, there is no absolute max in datasheet I looked at for Ib. But there
is a typical graph that looks like 20 mA would be acceptable.



Or you could do this :




The 10 ohms in MOSFET source to kill some damped oscillations of 2N7000.

The circuit has one drawback, the D2 circuit draws power when D2 off, eg.
this part of circuit always drawing power. One of the downsides.


Regards, Dana.

 

[bredniol]

AnalogKids point about running LED current thru base good caution.

Looking at a 2N3904, assuming your current is in range of 100 mA or
less, there is no absolute max in datasheet I looked at for Ib. But there
is a typical graph that looks like 20 mA would be acceptable.

View attachment 58440

Or you could do this :

View attachment 58442


The 10 ohms in MOSFET source to kill some damped oscillations of 2N7000.

The circuit has one drawback, the D2 circuit draws power when D2 off, eg.
this part of circuit always drawing power. One of the downsides.


Regards, Dana.

Thanks Dana,

what if my V+ (from which I'll also drive the gate) is 24V (15V in another version)? Would you simply go through a voltage divider before this circuit?

 

[danadak]

Divider or zener clamp with a R will do. Ignore the fact its illustrated with a NAND,
applicable to logic of MOSFET or.....



I would probably not use 470K, leakage concerns generating offset V, but general
idea correct.


Regards, Dana.

 

[bredniol]

leakage concerns generating offset V

Sorry I don't understand what you mean here

 

[danadak]

Say you have a simple cmos inverter, with a high valued R on its input, the
other side grounded. So you think the output should be at "1" level. But if
leakage from input protection circuitry, and surface leakage, get high enough
it could generate a "1" at input flipping the output to a "0", which usually a
designer does not want to happen. So a lower value of R prevents the
leakage from causing erroneous logic levels.


Regards, Dana.