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Cascading shift registers

V

valentin tihomirov

Jan 1, 1970
0
Call me a dumb but I cannot find any app notes on that. Are there any clock
implications, is it the major concern? When many registers hang on the same
clock line the open-collector controlled by degrades very quickly resulting
in too slow slope. I have tried NAND logic and it seems to work well. But
the clocking problems are hard-to-debug (they may appear occasionally) so i
want to be absolutely sure about the proper clock distribution. Should any
"specially designed drivers", schmidt triggers be used to rectify the signal
or the conventional logic gates, transistors are just good for this purpose?
What are the typical circuits?
 
L

Leon Heller

Jan 1, 1970
0
valentin tihomirov said:
Call me a dumb but I cannot find any app notes on that. Are there any
clock
implications, is it the major concern? When many registers hang on the
same
clock line the open-collector controlled by degrades very quickly
resulting
in too slow slope. I have tried NAND logic and it seems to work well. But
the clocking problems are hard-to-debug (they may appear occasionally) so
i
want to be absolutely sure about the proper clock distribution. Should any
"specially designed drivers", schmidt triggers be used to rectify the
signal
or the conventional logic gates, transistors are just good for this
purpose?
What are the typical circuits?

You should be OK until you exceed the fanout of the clock. It will be
dependent on the clock speed, as well.

Leon
 
T

Tim Shoppa

Jan 1, 1970
0
The problem is usually not the individual parts but the whole clock
distribution topology.

In some cases putting faster stiffer drivers on the lines will let you
do better with a questionable topology... but it's still a poor design.

Capacitive loading can also depend on construction technique as well as
topology. You mention "open collector", if you are using pull-up
resistors this pretty much guarantees capacitive loading slowing down
your clock transitions if you clock on the rising edge, and you'll
likely end up with problems of false triggering on a slow rising edge
even if you're clocking on falling edges.

The "classic" way of dealing with all this is to use equal-length
transmission lines and proper receivers and drivers for all clocks.
Tim.
 
J

John Larkin

Jan 1, 1970
0
Call me a dumb but I cannot find any app notes on that. Are there any clock
implications, is it the major concern? When many registers hang on the same
clock line the open-collector controlled by degrades very quickly resulting
in too slow slope. I have tried NAND logic and it seems to work well. But
the clocking problems are hard-to-debug (they may appear occasionally) so i
want to be absolutely sure about the proper clock distribution. Should any
"specially designed drivers", schmidt triggers be used to rectify the signal
or the conventional logic gates, transistors are just good for this purpose?
What are the typical circuits?


A shift register needs a fast clock edge to shift reliably; the clock
risetime should be comparable, or better less than, the propagation
delay of the flipflops inside the register. Any slow clock should be
cleaned up with a schmitt or something.

Between separate shift register chips, clock skew is fatal. If skew is
possible, add some delay (RC or some gate delays) between the Qn
output of each chip and the Din of the next, more delay than the max
possible clock skew.


John
 
K

krw

Jan 1, 1970
0
Between separate shift register chips, clock skew is fatal. If skew is
possible, add some delay (RC or some gate delays) between the Qn
output of each chip and the Din of the next, more delay than the max
possible clock skew.

Another "trick" is to route the clocks from the Qn (last FF) towards
the Q0 (first FF).
 
J

John Popelish

Jan 1, 1970
0
krw said:
Another "trick" is to route the clocks from the Qn (last FF) towards
the Q0 (first FF).

I have routed clocks the opposite direction of the data shift, with a
clock buffer between each register chip, so the propagation delays
occurred in opposite directions. Only two loads on each clock (one
register and one clock buffer).
 
K

keith

Jan 1, 1970
0
I have routed clocks the opposite direction of the data shift, with a
clock buffer between each register chip, so the propagation delays
occurred in opposite directions.
Exactly.

Only two loads on each clock (one register and one clock buffer).

That's fine if the clock nets are heavily loaded, though I propose that
it's not necessary to do both, since he clock buffers add delay.
 
V

valentin tihomirov

Jan 1, 1970
0
If skew is possible, add some delay (RC or some gate delays)

How do I know this in advance?
 
W

Wouter van Ooijen

Jan 1, 1970
0
Call me a dumb but I cannot find any app notes on that. Are there any clock
implications, is it the major concern?

1. The SRs will need a clear clock. This can easily be solved by
adding a ST buffer bufore each clock input. Note that some SRs have a
ST input.

2. When SRs are cascaded clock skew can be a big problem. The IMHO
best way to avoid this is using SRs with a delayed output, like the
4094.


Wouter van Ooijen

-- ------------------------------------
http://www.voti.nl
Webshop for PICs and other electronics
http://www.voti.nl/hvu
Teacher electronics and informatics
 
J

John Larkin

Jan 1, 1970
0
How do I know this in advance?


If the clock has a clean, fast rise time (and an open-collector won't)
and is routed to a small number of chips using short traces, it's
probably OK. Generally a logic level generated by a given logic family
is adequare to clock a small number (say, six?) devices of that same
logic family. Expect trouble splitting a simplistic shift register
across boards or scattering a lot of stages about a single board.

That's the basics. The details get into PCB trace impedances,
setup/hold time specs, signal integrity, stuff like that, the things
digital design engineers deal with.

John
 
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