V
valentin tihomirov
- Jan 1, 1970
- 0
Call me a dumb but I cannot find any app notes on that. Are there any clock
implications, is it the major concern? When many registers hang on the same
clock line the open-collector controlled by degrades very quickly resulting
in too slow slope. I have tried NAND logic and it seems to work well. But
the clocking problems are hard-to-debug (they may appear occasionally) so i
want to be absolutely sure about the proper clock distribution. Should any
"specially designed drivers", schmidt triggers be used to rectify the signal
or the conventional logic gates, transistors are just good for this purpose?
What are the typical circuits?
implications, is it the major concern? When many registers hang on the same
clock line the open-collector controlled by degrades very quickly resulting
in too slow slope. I have tried NAND logic and it seems to work well. But
the clocking problems are hard-to-debug (they may appear occasionally) so i
want to be absolutely sure about the proper clock distribution. Should any
"specially designed drivers", schmidt triggers be used to rectify the signal
or the conventional logic gates, transistors are just good for this purpose?
What are the typical circuits?