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### Network # Collector current

J

#### Jacky Luk

Jan 1, 1970
0
H.W help:
The early voltage is 60V in a common-emitter configuration for a npn bipolar
transistor. With Vbe = 0.65V and Vce = 1V collector current = 1.0mA, find
the collector current when Vbe = 0.67V and Vce = 9V

If i use the geometry thoery to calculate this,
I think i can approach to yielding the answer of this question. However when
Vbe's are different, the slope of these two curves are virtually different,
consider the
Slope of the device curve when Vbe = 0.65V
Vbe = 1mA / 60V + 1V where I would think of something similar to Vbe (when
0.67V) = Ic / 60V + 9V. Does the question offer too few or too many
parameters in solving the question?
but as stated in my book, using equation Ie = Ise * e ^ K * Vbe where K is
about 40V, I can yield the answer to be Ic = 1mA * Exp (40V -1 * 0.67V -
0.65V)
which is according to the first equation which states in my reference " it
shows that 10mV Increments correspond to increases in Ie and Ic by a factor
of exp (40V-1 * 0.01V) ".... then I feel the question is offering two many
parameters where some of them are not used???
Jack

R

#### Rich Grise

Jan 1, 1970
0
Jacky said:
H.W help:
The early voltage is 60V in a common-emitter configuration for a npn
bipolar transistor. With Vbe = 0.65V and Vce = 1V collector current =
1.0mA, find the collector current when Vbe = 0.67V and Vce = 9V
If Vcc is 60V, and Vce is 1V, and Ic = 1.0 mA, clearly Rl == 59K.

So, if with the change in base current, Vce= 9V, Il = Ic = 51/59K, or
0.864 mA.

Is that the answer the teacher wants?
If i use the geometry thoery to calculate this,
I think i can approach to yielding the answer of this question. However
when Vbe's are different, the slope of these two curves are virtually
different, consider the
Slope of the device curve when Vbe = 0.65V
Vbe = 1mA / 60V + 1V where I would think of something similar to Vbe (when
0.67V) = Ic / 60V + 9V. Does the question offer too few or too many
parameters in solving the question?
but as stated in my book, using equation Ie = Ise * e ^ K * Vbe where K is
about 40V, I can yield the answer to be Ic = 1mA * Exp (40V -1 * 0.67V -
0.65V)
which is according to the first equation which states in my reference " it
shows that 10mV Increments correspond to increases in Ie and Ic by a
factor of exp (40V-1 * 0.01V) ".... then I feel the question is offering
two many parameters where some of them are not used???
Jack

Good Luck!
Rich

J

#### Jonathan Kirwan

Jan 1, 1970
0
If Vcc is 60V, and Vce is 1V, and Ic = 1.0 mA, clearly Rl == 59K.

So, if with the change in base current, Vce= 9V, Il = Ic = 51/59K, or
0.864 mA.

Is that the answer the teacher wants?

Uh... He said "early voltage," Rich. This is an extrapolated point.

Jon

J

#### Jonathan Kirwan

Jan 1, 1970
0
Uh... He said "early voltage," Rich. This is an extrapolated point.

I should add that it is commonly found between 50V and 70V in NPNs, so the value
of 60V is right in the middle of that.

I think you completely missed the point of the student question, Rich.

Jon

R

#### Rich Grise

Jan 1, 1970
0
Jonathan said:
I should add that it is commonly found between 50V and 70V in NPNs, so the
value of 60V is right in the middle of that.

I think you completely missed the point of the student question, Rich.
Apparently so. Sorry for the misunderstanding.

But it still sounds like homework.

Cheers!
Rich

J

#### Jonathan Kirwan

Jan 1, 1970
0
But it still sounds like homework.

The question is almost certainly homework!

Jon

J

#### Jonathan Kirwan

Jan 1, 1970
0
Homework Question!
The early voltage is 60V in a common-emitter configuration for a npn bipolar
transistor. With Vbe = 0.65V and Vce = 1V collector current = 1.0mA, find
the collector current when Vbe = 0.67V and Vce = 9V
---

If i use the geometry thoery to calculate this,
I think i can approach to yielding the answer of this question. However when
Vbe's are different, the slope of these two curves are virtually different,
consider the
Slope of the device curve when Vbe = 0.65V
Vbe = 1mA / 60V + 1V where I would think of something similar to Vbe (when
0.67V) = Ic / 60V + 9V. Does the question offer too few or too many
parameters in solving the question?
but as stated in my book, using equation Ie = Ise * e ^ K * Vbe where K is
about 40V, I can yield the answer to be Ic = 1mA * Exp (40V -1 * 0.67V -
0.65V)
which is according to the first equation which states in my reference " it
shows that 10mV Increments correspond to increases in Ie and Ic by a factor
of exp (40V-1 * 0.01V) ".... then I feel the question is offering two many
parameters where some of them are not used???

You are very, very close, I can see.

For those not entirely clued in, here's the projection:

I(C)
|
|
| + -- V(BE)=0.67
| +
| + ^ . -- V(BE)=0.65
|+ . :
+ | . :
+ . | ^ :
+ . | : :
+ . | : :
<---+----------------------------0-------------------> V(CE)
60V 1V 9V
^
|
Early Voltage

Your computations are pretty much on the mark, I think. But keep in mind I'm a
hobbyist and have never taken a single class in electronics in my life. I read
and design small things, but that's all.

There are several ways to go at this, but one obvious factor is simply
projecting I(C) for V(CE)=9V, without dealing with the V(BE) change. That will
get you one piece of the way. Then, you need to deal with the impact of V(BE)
on that projected value. And you've got it almost right, there.

The projection is about the way I read you writing above. Namely, that the I(C)
at V(CE)=9V with V(BE)=0.65V would be a factor of ((60+9)/(60+1)) larger, based
only on the slope suggested by the Early voltage. Basic similar-triangle stuff,
as you suggest.

Next is that you need to deal with V(BE) and you can look at that from either a
e^(dV(BE)/V(t)) point of view (since V(BE) is large enough that the -1 can be
ignored) or else you can just remember that I(C) changes by a factor of 10 for
each 58.26mV (V(t)=q*T/k=25.3mV, variation ignoring the -1 is then V(t)*ln(10) =
58.2554mV or often shown as about 60mV) change in V(BE).

This is either:

change = e^(dV(BE)/25.3mV)

or,

change = 10^(dV(BE)/60mV)

Slight differences there, but your pick.

When you apply these together, the result is:

I(C)[@V(BE)=0.67V,V(CE)=9V] = 1mA * (VA+9)/(VA+1) * e^((0.67-0.65)/25.3mV)

Jon

A

#### Andyb

Jan 1, 1970
0
Jonathan Kirwan said:
The question is almost certainly homework!

The msg did start with "H.W. Help"

Andy

J

#### Jonathan Kirwan

Jan 1, 1970
0
I(C)[@V(BE)=0.67V,V(CE)=9V] = 1mA * (VA+9)/(VA+1) * e^((0.67-0.65)/25.3mV)

Shoot! Should have added that VA is the Early Voltage for the device, or:

VA = 60V

Sorry.

Jon

P

#### peterken

Jan 1, 1970
0
Well, this sounds a bit too theoretical for me having over 24 years of
practical R&D experience in upto chip design.... :-(

Given the fact every transistor has a tolerance in curves and Hfe, this
approach looks too far fetched, more like classroom-stuff, and never to be
used in real life.
Also, given the fact a transistor is implicitly a current-amplifier I wonder
who wants to calculate using Vbe voltages for a reference in a highly
tolerance-sensitive device

In every configuration, a transistor needs to be set using resistors for
having a known amplification to avoid unknown behaviour.
Starting point is using the *lowest* possible Hfe to begin calculations,
since *all* transistors of the same type will work then, despite of their
(most likely higher) Hfe.

Beginning in a reverse way, and assuming a minimum Hfe of say 100 (suitable
for most low signal low power transistors which are usually between
100-250), I can calculate Ib to be 10uA, and can assume Zbe to be 650mV/10uA
= 65k. (no resistor Re was given, I assume it to be zero)
I can also calculate Rc to be (60V-Vce)/ Ic = 59k

Assuming identical setup, I see a higher Vbe AND a higher Vce which is in
contradiction with the NPN-behaviour UNLESS Rc was modified.

Given the virtual 65k Zbe above, and assuming Vbe to rise to 0.67V Ib
becomes 0.67/65000 = 10.3uA
Assuming the same Hfe to be 100 again Ic would become 1,03mA
Ic would be then 60-(59k*1.03mA) = ERROR given the fact that 59k * 1.03mA =
60.77V
Transistor would be saturated for Rc = 59k!

Assuming Vce would indeed be measured 9V with Vbe = 0.67V then Rc was
modified to (60-9)/1.03mA = 49.514k

It might be possible top have slightly deriving values, but since as I say
transistors are HIGHLY tolerant devices....
In setup below I would at least implement an Re for stability and ease of
calculations.

greetz

H.W help:
The early voltage is 60V in a common-emitter configuration for a npn bipolar
transistor. With Vbe = 0.65V and Vce = 1V collector current = 1.0mA, find
the collector current when Vbe = 0.67V and Vce = 9V

If i use the geometry thoery to calculate this,
I think i can approach to yielding the answer of this question. However when
Vbe's are different, the slope of these two curves are virtually different,
consider the Slope of the device curve when Vbe = 0.65V
Vbe = 1mA / 60V + 1V where I would think of something similar to Vbe (when
0.67V) = Ic / 60V + 9V. Does the question offer too few or too many
parameters in solving the question?
but as stated in my book, using equation Ie = Ise * e ^ K * Vbe where K is
about 40V, I can yield the answer to be Ic = 1mA * Exp (40V -1 * 0.67V -
0.65V)
which is according to the first equation which states in my reference " it
shows that 10mV Increments correspond to increases in Ie and Ic by a factor
of exp (40V-1 * 0.01V) ".... then I feel the question is offering two many
parameters where some of them are not used???
Jack

S

#### Steve Evans

Jan 1, 1970
0
In every configuration, a transistor needs to be set using resistors for
having a known amplification to avoid unknown behaviour.
Starting point is using the *lowest* possible Hfe to begin calculations,
since *all* transistors of the same type will work then, despite of their
(most likely higher) Hfe.

Beginning in a reverse way, and assuming a minimum Hfe of say 100

I don't see how designing at the low-end range of Betas is going to
help much. If you do that and you end up in practice with a device
with a 300 Beta (not too unlikely) then either that stage or a
subsequent one is going to have so much current gain that the output
voltage across Rc is going to swing into the supply rail on one peak
and the base voltage on the other, leading to hideous distortion. I
don't see how it's possible to overcome the problem without measuring
each transistor's hfe individually and biasing accordingly.

Steve.

J

#### John Popelish

Jan 1, 1970
0
Steve said:
I don't see how designing at the low-end range of Betas is going to
help much. If you do that and you end up in practice with a device
with a 300 Beta (not too unlikely) then either that stage or a
subsequent one is going to have so much current gain that the output
voltage across Rc is going to swing into the supply rail on one peak
and the base voltage on the other, leading to hideous distortion. I
don't see how it's possible to overcome the problem without measuring
each transistor's hfe individually and biasing accordingly.

Assuming that linearity is your goal. it is possible to use the gain
of the transistor to produce a cancellation of the input signal, so
that the cancellation increases as the gain does. This obviously
gives the stage lass total gain, but stabilizes the variations caused
by gain variation.

The simplest example for a common emitter stage may be adding an
emitter resistor. The drop across this resistor effectively subtracts
from the voltage applied to the base. If the gain is higher, the
transistor passes a bit more current, but that causes more emitter
resistor drop which effectively lowers the voltage between base and
emitter. The more gain you are willing to give up, the more stable
the overall gain becomes.

K

#### Kevin Aylward

Jan 1, 1970
0
Steve said:
I don't see how designing at the low-end range of Betas is going to
help much.

It does. Thats the way its done.
If you do that and you end up in practice with a device
with a 300 Beta (not too unlikely) then either that stage or a
subsequent one is going to have so much current gain that the output
voltage across Rc is going to swing into the supply rail on one peak
and the base voltage on the other, leading to hideous distortion.

It wont if you design it *correctly*. One designs the circuit so that
the circuit is essentially insensitive to hfe as far as bias current
goes. To do this one might have a bleed current that is calculated
knowing the worst case base current and making it a good bit larger.
Secondly, for example, if the transistor is driving an output load it
will need a minimum base drive drive. If the hfe is larger, it wont
matter, it only takes the current it needs, e.g. emitter follower. Only
if the drive runs out of steam, will there be a problem.
I
don't see how it's possible to overcome the problem without measuring
each transistor's hfe individually and biasing accordingly.

The issue is designing bias circuits that are insensitive to hfe. This
usually require designing based on the minimum hfe expected. One makes a
base potential that is essentially indepednant of base current. If the
bleed current (resister from base to ground) is say 10 times the minimum
base current, the base voltage wont change much. Assuming there is a
resister in the emitter (class A amp), then this voltage will also be
independent of base current. The voltage across this resister will fix
the emitter current.

http://www.anasoft.co.uk/EE/bipolardesign3/bipolardesign3.html
http://www.anasoft.co.uk/EE/index.html

Kevin Aylward
[email protected]
http://www.anasoft.co.uk
SuperSpice, a very affordable Mixed-Mode
Windows Simulator with Schematic Capture,
Waveform Display, FFT's and Filter Design.

P

#### peterken

Jan 1, 1970
0
Steve
Fair enough.... but :
Ever heard of the basic classroom-stuff that amplification of a transistor
can be calculated by the formula A=Rc/Re ?
In this formula NO Hfe is ever mentioned, neither for a Hfe of 100 of a Hfe
of 300.
Result: Hfe independent amplification, thus *known* behaviour for *every*
transistor of the same type in a given setup, thus *no* saturation effects
unless the inputsignal is over expected levels.
Only purpose of using *lowest* possible Hfe is to calculate Rb and Re for a
given device, thus using *worst case* conditions for a given setpoint.
If designing correctly this way, all tolerances will cancel themselves,
*even* temperature-dependent tolerances....
Of course, things get a bit different if you want to use a thermometer using
a bad-setup transistor... it really works ya know (AND is used for
temperature-compensation of power stages) ;-)

Real world has several things many schools won't tell, only years of
practice shows them

And as I stated I really don't see any practical use of the initial
calculation given in this thread since no-one ever uses it in real world as
far as I see it
(Or at least I never saw the initial calculations coming up during 24 years
of R&D experience, not by myself nor any of my colleagues)

In every configuration, a transistor needs to be set using resistors for
having a known amplification to avoid unknown behaviour.
Starting point is using the *lowest* possible Hfe to begin calculations,
since *all* transistors of the same type will work then, despite of their
(most likely higher) Hfe.

Beginning in a reverse way, and assuming a minimum Hfe of say 100

I don't see how designing at the low-end range of Betas is going to
help much. If you do that and you end up in practice with a device
with a 300 Beta (not too unlikely) then either that stage or a
subsequent one is going to have so much current gain that the output
voltage across Rc is going to swing into the supply rail on one peak
and the base voltage on the other, leading to hideous distortion. I
don't see how it's possible to overcome the problem without measuring
each transistor's hfe individually and biasing accordingly.

Steve.

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