This is becoming an interesting discussion. From what I can understand, the
emitter cap is there to shunt (if that's the right word) certain frequencies
to ground so they don't get amplified.
Like I said before, I don't really understand the use of the topology shown at
that site. Given what they drew there, of course, as the frequency increases,
the shunting gets more pronounced.
But the problem as I see it in that example is that if the capacitor is sized to
effectively bypass the emitter R at some low frequency and for those frequencies
above that point (until other factors dominate and change what I'm about to
say), then the emitter is essentially grounded above that frequency point. So,
let's say you size it to bypass the emitter R at 100Hz and above, then for those
frequencies the Z of the capacitor will be diminishingly tiny and the emitter
will be, in effect, at ground.
This isn't a good thing, usually. What it means is that the gain is then based
on R(C)/(r(e)+Z(c-bypass)) and, since r(e) is highly dependent on I(C), the gain
will be varying all over the place. Similarly, if the Z of the capacitor hasn't
yet diminished to the point where it is very much smaller than r(e) itself, then
the frequency will also be varying the gain all over the place, too.
It's not good.
But when you figure out the cap, you
have to use the lowest frequency you wish to eliminate (shunt?)
You would use the lower frequency that you want to shunt, yes. But that is the
reverse way to look at it. You are actually setting the lower end of the
__desirable__ frequency band. Frequencies less than this will get smaller gains
and will therefore diminish in their relative presence in the output because
they are NOT bypassed by the C.
Here's a better topology (not the only one, though):
V+ V+
| |
| |
| |
\ \
/ Rb1 / Rc
\ \
| |
| +--------> OUT
| |
| |
| b|/c Q1
+-------| NPN
| |\e
IN >-----+ v
| |
| +-------,
| | |
| | \
| | / Rac
| \ \
\ / Re |
/ Rb2 \ |
\ | |
| | --- Cac
| | ---
| | |
| | |
--- --- ---
gnd gnd gnd
Without getting into more complex models, gain is:
Rc / ( r(e) + ( Re || (Rac + Z(Cac)) ) )
Here, you can see that Cac acts similarly, but that when its Z is tiny, then the
resulting gain is set by Rc/(r(e)+(Re||Rac)). (|| means the parallel equivalent
resistance.)
In other words, you design the DC operating point by ignoring Rac and Cac, at
first. Once the DC operating point is established in that way, then you design
Rac and Cac so that when the frequency rises above some given point, Cac will be
an effective bypass, tying Rac to ground. But NOT the emitter itself!
That way, you can design this to have a predictable gain that doesn't vary much
over I(C) or over frequency, once that low frequency is reached (and beyond)
because you can arrange things so that (Re||Rac) is still large compared with
r(e) "little r-e" and also that Rac is large compared to the Z of Cac at and
above some design frequency. Since (Re||Rac) also isn't dependent on the
frequency at all because the Z of Cac is also diminishingly tiny by comparison,
the gain can be made relatively stable over a wide range of frequencies.
and then
all frequencies higher than that also get eliminated. So is it sort of a
low pass filter?
No, the other way around. Since frequencies lower than this set a high Z, the
gain of the amplifier at those still lower frequencies declines until the Z is
very much greater than the emitter resistor and that emitter resistor then sets
the low gain limit. Since higher frequencies have a higher gain (and in that
web site's design, a continually rising gain that doesn't make sense, usually),
they appear more dramatically in the output.
One other thing I noticed about using their equations is
that the emitter resistor is almost always 10% of the collector resistor.
Well, in general, you usually want some gain! If the emitter resistor were
larger, you'd be attenuating the signals instead of increasing them. Sometimes,
that's what you want. But not here, I think.
I
started using their method because I didn't know how to calculate the bias
voltage divider for some transistors I couldn't find the curves for.
I went through some of the calculation steps in detail, earlier. Did you read
them? Did they make any sense? Also, most small transistors (BJTs) can work
just fine on a quiescent I(C) of anywhere from 0.4mA to 20mA, and probably even
wider than that. If you want to just play and aren't designing anything in
particular, I'd pick a quiescent I(C) of 1mA and build up a circuit on that
basis.
Like others have pointed out, a real design will need to account for what is
driving the circuit and what the circuit is supposed to drive, itself. For
example, if you are driving your 'test' amplifier circuit from an oscillator or
even a square wave generator, then how are you going to hook that up? Do you
imagine just tying one end to ground and the other end to the supposed input at
the BJT base? Through a resistor of some kind? Through a capacitor of some
value? How? And some inputs, like say a microphone or some other kind of
transducer, may have very particular requirements in order to operate well.
Usually, you have some kind of circuit designed to accommodate your transducer
and allow it to operate well. So that circuit is designed to meet the need of
the transducer and reflect the signal accurately into the next stage, which
often IS designed for some gain. But the first stage/circuit is more designed
for the transducer. Then you might have several stages of voltage amplification
after that. Finally, followed by yet another circuit designed for the type of
output transducer -- for example, such as a speaker. That last stage will again
be tailored for the output transducer and not for voltage gain, itself.
In the above case example I gave, where the amplifier is designed for voltage
gain at some AC frequency and above, it might look more like:
V+ V+
| |
| |
| |
\ \
/ Rb1 / Rc
\ \
| |
| +--------> OUT
| | (perhaps to another capacitor input)
| |
| b|/c Q1
+-------| NPN
|| | |\e
IN >----||---+ v
|| | |
| +-------,
Cin | | |
| | \
| | / Rac
| \ \
\ / Re |
/ Rb2 \ |
\ | |
| | --- Cac
| | ---
| | |
| | |
--- --- ---
gnd gnd gnd
Cin would be sized, like Cac, to pass frequencies above some point very well.
Using a capacitor there allows the DC biasing network to do it's job and
correctly bias Q1 and to maintain that bias as higher frequency signals are
passed on by Cin. Any DC setpoint from the input side of Cin won't pull down or
pull up the DC biasing -- it will simply charge Cin and leave it charged.
Then I
started to incorporate all their equations into my spreadsheet so that now I
can build one from input to output. They made it easy, all you need to enter
is the hfe, Vcc, desired collector current and frequencies to pass.
I've done similar things with LTSpice.
Jon