They do produce the "same" output only if you look at the outputs in a coarse fashion, meaning the steady state between clock pulses.
On a synchronous counter all outputs change at the same time (neglecting small differences in propagation delay of individual flipflops) becausee all flipflops are triggered by the same clock.
In an asynchronous counter only one flipflop (the Least significant bit = LSB) is triggered by the clock. The outer flipflops are triggered by the output of the preceding flipflop each. Thus the count ripples or propagates through the chain of flipflops. That is why you see glitch in the asynchronous circuit (and you should be able to see the rippling count if your time resolution is increased).
In the extreme case the LSB will be triggered before the MSB (most significant bit) has changed. This happens if the clock period is as long as the propagation delay of the flipflop chain. In this case the counter never reaches the steady state.
Harald