# CPLD HDL?

W

#### Winston

Jan 1, 1970
0
I want to put my latest idea in a PLD to save board space.
Years ago I was comfortable working in PALASM, CUPL and ABEL.
I also documented another guy's Verilog source.

but it is said to have 'limited' simulation ability.
There are addon$available that have complete simulation ability. My Question Without Intending To Start A Religious War: What modern HDL compiler and simulator package has: The ability to run on Linux A gentle learning curve Good user support Fast, easy use Efficient use of PLD resources Support for multiple part vendors Reasonable purchase price ..and all other characteristics of a superior product. Thanks! --Winston W #### Winston Jan 1, 1970 0 as far as I remember the limits is that with more than 1000 lines of code simulation gets slowed down, and code for xilinx blocks doesn't count, Not a big problem with a cpld sized design you could always use a free simulator like e.g Icarus and GTKWave don't know if multiple vendor is really available -Lasse OK. Thanks! --Winston W #### Winston Jan 1, 1970 0 Jon said: I run the free webpack version on some systems, the "limits" have never bothered me, I use modest FPGAs and CPLDs. Runs well on Linux. The only thing I know doesn't work is printing schematics, which I don't use much, anyway. CPLDs will not have very big HDL files, maybe 1-2 pages. I use VHDL, you can also use Verilog. Hmmm, not so sure about user support. You get email support with the free tools, and phone support with the paid tools, but their phone support is pretty awful, or was the last few times I called. I ended up diagnosing the problems myself and telling THEM how to fix it! I think the efficiency is good but have nothing to compare it to. But, expensive packages use Xilinx back-end tools to do place and route. Obviously, Xilinx tools don't support other vendors. Thanks, Jon. Sounds like I ought to contemplate a microcontroller implementation instead. Then I could use assembly, which I find entertaining. --Winston N #### Nico Coesel Jan 1, 1970 0 Winston said: I want to put my latest idea in a PLD to save board space. Years ago I was comfortable working in PALASM, CUPL and ABEL. I also documented another guy's Verilog source. I see that Xilinx offers their ISE WebPACK suite for free but it is said to have 'limited' simulation ability. There are addon$ available that have complete simulation
ability.

My Question Without Intending To Start A Religious War:

What modern HDL compiler and simulator package has:
The ability to run on Linux
A gentle learning curve
Good user support
Fast, easy use
Efficient use of PLD resources
Support for multiple part vendors
Reasonable purchase price

I use Xilinx' free webpack for their CPLDs. Their XC9500 series is
pretty cheap. As a language I use VHDL because... I know VHDL. For
simulation I use ghdl (ghdl.free.fr).
..and all other characteristics of a superior product.

Not on this world...

W

#### Winston

Jan 1, 1970
0
Jon said:
Winston wrote:

Well, I do a lot of stuff where micros may be too slow,
or not parallel enough. VHDL is pretty easy to pick up.
And, you CAN enter a schematic, even in familiar 74xx
part numbers, wire it all up and have it turned into logic
on a CPLD or FPGA. Some interface glue projects I still
do it that way, although I am moving more and more to HDL.

Jon

Tim > Oh, don't give up now, I was hoping to harvest ideas
Tim > from this thread for a board that's already got four
Tim > 74AHCxx parts on it, and seems to be acquiring more!!!

Jon, Tim and I would very much like to know what package
you use to capture a schematic and output (JEDEC?) for a
CPLD or FPGA. Is the ghdl package Nico mentioned involved?

Thanks

--Winston

N

#### Nico Coesel

Jan 1, 1970
0
Phil Hobbs said:
I haven't done a PLD in quite awhile--my current toolset is Orcad PLD
for DOS. They're great for stuff where you need better timing
coherence than the processor can give you, e.g. sampling.

I guess a good book with actual examples, not just a language
specification Just make sure it covers writing functions and so
on. There is a lot of power in VHDL. In the past I've often designed
pieces of logic which can be configured for different widths,
channels, etc. That took some studying to get it right but it has paid
off big time in several occasions. It helps if you have a programming
background.

There is also Verilog but I never understood Verilog. It makes me feel
like I'm looking at a netlist output from a schematic.

M

#### Mr.CRC

Jan 1, 1970
0
Winston said:
I want to put my latest idea in a PLD to save board space.
Years ago I was comfortable working in PALASM, CUPL and ABEL.
I also documented another guy's Verilog source.

but it is said to have 'limited' simulation ability.
There are addon\$ available that have complete simulation
ability.

My Question Without Intending To Start A Religious War:

What modern HDL compiler and simulator package has:
The ability to run on Linux
A gentle learning curve
Good user support
Fast, easy use
Efficient use of PLD resources
Support for multiple part vendors
Reasonable purchase price
..and all other characteristics of a superior product.

I use Xilinx Webpack on Linux, and the Icarus Verilog simulator.

Gentle learning curve just doesn't apply to Xilinx software.

I suppose support is good if you use Xilinx or Altera, between the
USENET and manufacturer forums. I rarely need support, and even when I
do it's just to save some time rather than figure it out myself.

I've never taxed any of my PLDs enough to care about very high efficiency.

Support for multiple vendors? Well, that will only happen if you aren't
using the software from one of the manufacturers. I don't go there, due
to too high prices, which I prefer free.

Good luck and have fun.

W

#### Winston

Jan 1, 1970
0
Mr.CRC wrote:

(...)
I use Xilinx Webpack on Linux, and the Icarus Verilog simulator.

Gentle learning curve just doesn't apply to Xilinx software.

Holey Cannolli! In the Good Old Days, you just supplied a source
file and told the compiler to get started. The tutorial
has me doing all kinds of gyrations, referring to unlabeled
windows and sending me on a goose chase to locate buttons that
are not visible on the existing screen, all with no explanation
of *why* these things need to be done. Wow!
I suppose support is good if you use Xilinx or Altera, between the
USENET and manufacturer forums. I rarely need support, and even when I
do it's just to save some time rather than figure it out myself.

I've never taxed any of my PLDs enough to care about very high efficiency.

Support for multiple vendors? Well, that will only happen if you aren't
using the software from one of the manufacturers. I don't go there, due
to too high prices, which I prefer free.

Good luck and have fun.

Thanks, Mr. CRC

--Winston

J

#### Jeroen Belleman

Jan 1, 1970
0
o said:
[...] VHDL is pretty easy to pick up.

Cheers

Phil Hobbs
IMO, the easiest way is to have a look at a book that teaches digital
design presenting simultaneously the conventional and the VHDL approach.
For instance, the first half of P. J. Ashenden's "Digital Design, an
Embedded Systems Approach Using VHDL". It seems there is the same book
with Verilog.

The most common error when learning VHDL is to start thinking of it in
software terms: since VHDL is a programming language, with constructs
which are very similar to conventional languages, it is easy to forget
that you are actually using it for a very specific subset of its
abilities: to describe hardware. As you already know digital design,
this will not be a problem for you, but it IS a problem with students.

Pere

I have little trouble translating VHDL code in mind-images of logic
circuitry, but I find its syntax clumsy and baroque. I can't
seem to get used to "if signal = '1' then" as opposed to
"if signal then", or "<=" rather than just "=", not to mention
that "<=" means different things inside or outside of processes.
And the inconsistency of "elsif" vs. "end if", or the difference
between "if" and "when" statements, etc, etc.

Also, I see many people, even those fluent in VHDL, draw little
circuit diagrams before translating them into VHDL.

I think VHDL is a crutch, just like the 1984 rectangular logic
gate symbols were a crutch for immature plotting software.

Jeroen Belleman

N

#### Nico Coesel

Jan 1, 1970
0
o pere o said:
IMO, the easiest way is to have a look at a book that teaches digital
design presenting simultaneously the conventional and the VHDL approach.
For instance, the first half of P. J. Ashenden's "Digital Design, an
Embedded Systems Approach Using VHDL". It seems there is the same book
with Verilog.

The most common error when learning VHDL is to start thinking of it in
software terms: since VHDL is a programming language, with constructs

Actually you should treat it like a programming language and a design
as a software problem. If you keep thinking in logic then you end up
inputting a netlist with VHDL. VHDL gets very clumsy that way (lots of
typing).

For fun: use google to find a VHDL implementation of a priority
encoder. 9 out of 10 people write an if statement for each output
(which gets large quickly). Only one writes a clever three line
function which works regardless the number of input bits.

The problem students have is not with logic design but with the fact
that VHDL describes a parallel process and that every line of code is
executed simultaneously.

N

#### Nico Coesel

Jan 1, 1970
0
o pere o said:
If you go this way, it can quickly become very fun indeed, especially
when you end up using a huge number of resources. Yes, optimizers do
work (more or less), but you should only trust them when you already
have an approximate idea of what the outcome should be (and this is not

Thats part of getting experienced. Programmable logic manufacturers
often have documents describing what is efficient for their devices
and what is not.
Because they loose the connection of the language with the underlying
hardware!

That is the purpose of a high level language. When I program in C I
don't care how many instructions it uses. As long as the program works
fast enough and fits in the flash it is OK.

W

#### Winston

Jan 1, 1970
0
MK wrote:

(...)
Hello - This thread is so Xilinx centric !

Have a look at Lattice - their free tool is based on Aldec HDl which is nice (Schematic, VHDL and Verilog in one
simulator -I have the paid for version but the free one is OK for small stuff).

Lattice have a much better offering than Xilinx (IMHO) for small FPGA and PLD/FPGA crossover parts.

--Winston

J

#### John Devereux

Jan 1, 1970
0
Phil Hobbs said:
That's an overstatement, I think. Since MCU cost depends strongly on
the flash size, knowing how to make the code smaller is economically
important. (It's especially important whey you're already using the
biggest version of your processor, of course.)

Hi Phil,

On microcontrollers what you often find is that a large chunk of the
program size turns out to be consumed by a few large library
functions. Sometimes ones you did not even realise you referenced.

And the reason say the ARM compiler might beat gcc on size is that their
libraries are better optimised, not because its detailed code generation
is significantly improved.

For smaller projects I find I am better off not using the traditional C
library at all. It is more trouble than it is worth. An innocent
"#assert" brings in a full floating point printf and all of stdio, and
suddenly your 64k flash is full.

Over time I have built up a library containing replacements for the very
few C library functions that are any actual use (in a small embedded
system context).

N

#### Nico Coesel

Jan 1, 1970
0
Phil Hobbs said:
That's an overstatement, I think. Since MCU cost depends strongly on
the flash size, knowing how to make the code smaller is economically
important. (It's especially important whey you're already using the
biggest version of your processor, of course.)

True, but ask yourself: are you going to tinker with assembler or make
the algorithm more clever so it is faster or smaller?

Sometimes there is a third option. With the ARM7TDMI controllers (the
non-Cortex ones) you have a choice to use the thumb instruction set or
the bigger ARM instruction set. For one project I had to cram a TCP/IP
stack, DNS, DHCP, webserver and some other stuff into 32kB flash. I
opted to use the thumb instruction set. That saved lots of memory at
the expense of having to write some assembly to handle interrupts.

And is the price of the MCU really the only driving parameter? Leaner
programming often means spending more time (and the amount of time
goes up exponentially). In my experience people often look too much to
the price of the parts and forget about the time required to make the
firmware. Once a product sells by thousands you can still do a
redesign to cut the costs.

N

#### Nico Coesel

Jan 1, 1970
0
John Devereux said:
Hi Phil,

On microcontrollers what you often find is that a large chunk of the
program size turns out to be consumed by a few large library
functions. Sometimes ones you did not even realise you referenced.

And the reason say the ARM compiler might beat gcc on size is that their
libraries are better optimised, not because its detailed code generation
is significantly improved.

For smaller projects I find I am better off not using the traditional C
library at all. It is more trouble than it is worth. An innocent
"#assert" brings in a full floating point printf and all of stdio, and
suddenly your 64k flash is full.

I like to stay Posix compliant so existing pieces of code can be used
directly and other people can get up to speed quickly. The C library
which comes with mspgcc is pretty compact and its easy to get it
compiled for ARM. I have been using that library ever since I moved
from MSP430 to ARM.

If the printf from the mspgcc libc gets too big I rather create a
minimal version of printf than writing my own non-standard printing
routines.

Here is an example of a minimal printf:
http://users.powernet.co.uk/eton/kandr2/krx703.html

In some space constrained projects of mine it just supports decimal
and hex without any formatting.

W

#### Winston

Jan 1, 1970
0
(...)

maybe I'm strange or have used xilinx too long, but I find rather
straight forward;

open new project, choose name, location, part, etc.
add new source file, verilog module, add some ports if you like,
or do it later in the text editor

code code code ....

and new source, verilog test fixture,

code testbench...

run simulator, fix bugs

user constraints, assign what pins to what ports

implement design

configure device, done ...

It's easy after the first 25!

--Winston

J

#### John Devereux

Jan 1, 1970
0
I like to stay Posix compliant so existing pieces of code can be used
directly and other people can get up to speed quickly. The C library
which comes with mspgcc is pretty compact and its easy to get it
compiled for ARM. I have been using that library ever since I moved
from MSP430 to ARM.

If the printf from the mspgcc libc gets too big I rather create a
minimal version of printf than writing my own non-standard printing
routines.

Here is an example of a minimal printf:
http://users.powernet.co.uk/eton/kandr2/krx703.html

Uh - that one seems to call printf so does not seem a great amount of
use on it's own?!

But yes I started out with a public-domain printf and added a few things
to it (like support for "fixed-point" format specifiers).

N

#### Nico Coesel

Jan 1, 1970
0
John Devereux said:
Uh - that one seems to call printf so does not seem a great amount of
use on it's own?!

Ofcourse you substitute those with functions that dump the contents to
the console as chars . There is a much better 'skeleton' but I

W

#### Winston

Jan 1, 1970
0
Jon said:
Winston wrote:

No JEDEC format for FPGAs. At least up to a point, the
Xilinx web pack had schematic entry and libraries for their
various chips. They MAY have dropped schematic at some point
fairly recently. Schematic still works on 10.1, which we still use
because it has support for 5V XC9500 and Spartan 2E.

You need to know that while you may enter a schematic, it
will be broken down into equations and resynthesized into
very different logic to best fit the CPLD or FPGA architecture.
The FPGAs get a "bit" file, which can be converted to a
memory image to be put into an EPROM. The Spartan 3AN
and CPLDs have flash memory on-chip to hold the configuration
info. I program the CPLDs using a Xilinx parallel port JTAG
pod, there is newer and better USB stuff now, but this still works.
I have not used ghdl, I just use the Xilinx tools on Linux.
They have an integrated environment that works, but may not be the
most wonderful. So,you get schematic entry, VHDL and Verilog
synthesis, simulation from the HDL, simulation from the
synthesized logic, and a bunch of other tools to examine
the timing results, edit pin lists and timing constraints
and a bunch of other stuff. You can actually track your signals
through the logic fabric, which can sometimes be instructive when
things are not communicating properly on-chip.

On FPGAs you can synthesize a mini-logic analyzer on chip
(Chip Scope) and read it out via JTAG to track problems that
can't be solved with simulation.

Jon

Thanks a lot for this info
and that in your other post, Jon.
I find it extremely valuable.

--Winston

K

#### [email protected]

Jan 1, 1970
0
Is there an equivalent to K&R for VHDL?

I had a pretty good one but someone swiped it (and I don't remember the name).
:-(

The subset of VHDL used for synthesis is pretty easy to pick up. The entire
language, not so much. Learn it as you need it.

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