Maker Pro
Maker Pro

Debouncing....at About 1Mhz

D

D from BC

Jan 1, 1970
0
On Fri, 02 Nov 2007 20:26:21 -0700, John Larkin

[snip]
When we bought our building, it was a working fortune-cookie factory,
owned by the Louie family.

http://s2.supload.com/free/FortCookMach.JPG/view/

They gave us a couple of big boxes of cookies with the building, and
here were the first two I opened:

http://s2.supload.com/free/Fortunes.jpg/view/

Google "Louie Fortune Cookie Machine" for some history.

John

All fortune cookies are so positively biased.

What if people got these in fortune cookies :)

"Leave a big tip for extra luck"
"Please check another fortune cookie"
"Game piece 27...Get all pieces and win a free fortune cookie"
"Only 21 calories!"
"For success, do not read this fortune cookie"
"Fortune cookie business for sale. Only $44000. Call ***.***"
"Get 2x larger see www.bazookapenis.com"
"You've opened our 1millionth fortune cookie!"
"Medium size. Wash in luck warm water. No ironing."


D from BC
 
J

John Larkin

Jan 1, 1970
0
Here's what I've finally coughed up... :O *

http://www.members.shaw.ca/chainsaw/SED/DfromBCdebounce.jpg
547Kb slightly crappy LTSpice screen capture

Notes
------
* Circuit not reduced yet...
* RC values, gate prop, generators will all be adjusted later for
proper timing.
* I chose this timing just to use the default gate parameter
settings..(laziness).
* 1st time doing so much digital in LTSpice... (Most of my digital is
done in CM2000)


Circuit Description
-------------------
D latch A2 latches on 1st positive edge
D latch A1 latches on 1st negative edge

Each latch triggers a one-shot circuit which resets the neighboring
latch.
Each one shot period is just slightly longer than the bounce period.


It looks like it works...

Open to comments or feedback...

D from BC

Well, there's 4 prop delays from the falling edge input to the output.

And not to be *too* critical, but this is a classic hazard-filled
spaghetti-code glitch-driven asynchronous mess. For example, a fast
glitch can fire both flipflops. And the circuit has four internal
states, one of which is a hangup state, with both flops set; it will
probably manage to find its way into that situation, and can never get
out.

My circuit is better because it has no unnecessary states, and because
it's simple and easy to understand. Much faster, too. The
lowpass+schmitt is even better if you can tolerate the delay.

Asynchronous circuits are inherently hazardous, and desperately *want*
to screw up, so should be kept as simple as possible.

John
 
D

D from BC

Jan 1, 1970
0
This has got to be a classic signal clean up problem....

I need a circuit that triggers on edge A, then ignores about 0.1uS of
jitter then triggers on edge B and then ignores a following 0.1uS of
jitter.

+-+ +-+ +----------------+ +-+ +-+
In | | | | | | | | | |
A | | | | B | | | |
-------+ +-+ +-+ +-+ +-+ +-----------

|<0.1uS>| |<0.1uS >|
|< 0.5uS >|


Out +------------------------+
| |
A' B'
-------+ +-------------


Edge A to A' is ~ less than 10nS
Edge B to B' is ~ less than 10nS

All values are approximates.
"In" and "Out" are repeating waveforms.

I think I can do it with:

1 flip flop
1 >0.1us delay circuit
Sprinkled with gates..

Or maybe I need 2 flip flops..one for edge A and one for edge B..

I'm not even sure yet which type of FF to get.

If anybody has done this problem before and doesn't mind sharing..let
me know a topology...

In the meantime, I'll be doodling until I get a solution...


D from BC


Here's what I've finally coughed up... :O *

http://www.members.shaw.ca/chainsaw/SED/DfromBCdebounce.jpg
547Kb slightly crappy LTSpice screen capture

Notes
------
* Circuit not reduced yet...
* RC values, gate prop, generators will all be adjusted later for
proper timing.
* I chose this timing just to use the default gate parameter
settings..(laziness).
* 1st time doing so much digital in LTSpice... (Most of my digital is
done in CM2000)


Circuit Description
-------------------
D latch A2 latches on 1st positive edge
D latch A1 latches on 1st negative edge

Each latch triggers a one-shot circuit which resets the neighboring
latch.
Each one shot period is just slightly longer than the bounce period.


It looks like it works...

Open to comments or feedback...

D from BC
 
J

John Larkin

Jan 1, 1970
0
Brutal! :)

Yup... I now see that 4 prop delay from the falling edge input to the
output.
Darn..

My spaghetti needs a bandaid. :)


No, it needs to be simpler.

I know guys who would say "gee, I can add a hang-state detector that
senses when both flipflops are set for some time interval, then resets
both of them."

John
 
D

D from BC

Jan 1, 1970
0
Here's what I've finally coughed up... :O *

http://www.members.shaw.ca/chainsaw/SED/DfromBCdebounce.jpg
547Kb slightly crappy LTSpice screen capture

Notes
------
* Circuit not reduced yet...
* RC values, gate prop, generators will all be adjusted later for
proper timing.
* I chose this timing just to use the default gate parameter
settings..(laziness).
* 1st time doing so much digital in LTSpice... (Most of my digital is
done in CM2000)


Circuit Description
-------------------
D latch A2 latches on 1st positive edge
D latch A1 latches on 1st negative edge

Each latch triggers a one-shot circuit which resets the neighboring
latch.
Each one shot period is just slightly longer than the bounce period.


It looks like it works...

Open to comments or feedback...

D from BC

I've noticed the IE seems to butcher this image at my end...I suspect
image resize distortion.
When I view the file using windows picture viewer, the image looks
fine.
Viewing might be better on a webpage
http://www.members.shaw.ca/chainsaw/SED


D from BC
 
D

D from BC

Jan 1, 1970
0
Well, there's 4 prop delays from the falling edge input to the output.

And not to be *too* critical, but this is a classic hazard-filled
spaghetti-code glitch-driven asynchronous mess. For example, a fast
glitch can fire both flipflops. And the circuit has four internal
states, one of which is a hangup state, with both flops set; it will
probably manage to find its way into that situation, and can never get
out.

My circuit is better because it has no unnecessary states, and because
it's simple and easy to understand. Much faster, too. The
lowpass+schmitt is even better if you can tolerate the delay.

Asynchronous circuits are inherently hazardous, and desperately *want*
to screw up, so should be kept as simple as possible.

John

Brutal! :)

Yup... I now see that 4 prop delay from the falling edge input to the
output.
Darn..

My spaghetti needs a bandaid. :)


D from BC
 
W

whit3rd

Jan 1, 1970
0
This has got to be a classic signal clean up problem....

I need a circuit that triggers on edge A, then ignores about 0.1uS of
jitter then triggers on edge B and then ignores a following 0.1uS of
jitter.
I need a circuit that triggers on edge A, then ignores about 0.1uS of
jitter then triggers on edge B and then ignores a following 0.1uS of
jitter.
[where edge A is low-to-high and B is high-to-low]

So, use a nonretriggerable monostable with rising clock to
make a pulse at A, another with falling clock to make a pulse
at B, and Set/Reset a flop flop with those. Use the monostable A
output to gate (inhibit) the B trigger, and the B output to gate the
A trigger. As long as the monostable time
is set longer than the jitter window, you're golden.
Well, the trigger/output propogation delay has to be shorter than
the delay to first false transition...

For retriggerable monostables, the extra edges will stretch the
output pulse; if the stable time is guaranteed longer than the
monostable period, that's OK too.

The nonclassic solution is filtering followed by a Schmitt trigger.
That introduces phase delay, of course, and senses some average
over time rather than the initial edges.
 
J

John Fields

Jan 1, 1970
0
Oh oh...looks like the road gets bumpy around 10nS...

I'd rather get off the logging road and steer back onto the highway
with the low speed limit.

I'd go for the best that can be done with the 74X series to start.
That <10nS time is based on 1/10th of the total of other delays in my
system. So..It can be relaxed.

I could handle up to 100nS of edge delay but the circuit loses it's
'cool' appeal.

---
It's not 'it's', it's 'its'.

So, you were asking for something frivolously, disregarding the
investment in time someone seriously interested in helping you would
have to expend in order to meet your ~10ns "requirement", when that
10ns spec was just there to make you look "cool" in your bosses'
eyes?
---
Like driving a bicycle instead of a motorcycle. :(

---
First you need to learn to walk.
---
I can probably do a ultra fast version another day.

---
Don't you mean that you can ask someone to do an ultra fast version
for you another day?

Anyway, here's the simulation I promised you, in LTSPICE:

Version 4
SHEET 1 1924 1060
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TEXT -1608 896 Left 0 !.tran .5
TEXT -1344 -376 Left 0 ;SIGNAL GENERATOR
TEXT -184 -376 Left 0 ;DEBOUNCER
TEXT 512 448 Left 0 ;OUTPUT

The concept is there, and it works, so all you need to do is convert
the circuit to a TTL equivalency, if that's what you want to use,
and maybe use some diodes instead of gates to get the chip count
down.

You know how to do that, right?

Larkin's down to two chips, but he's got a lot of RFI going on since
every transition of the input signal generates spikes all through
his delay network and into the air.
 
D

D from BC

Jan 1, 1970
0
No, it needs to be simpler.

I know guys who would say "gee, I can add a hang-state detector that
senses when both flipflops are set for some time interval, then resets
both of them."

John

Actually.. I've been neglecting to watch out for a freeze up problem.

I had another bandaid in mind..

The bandaid was adding 2 NAND gates and a SR to my cct on
http://www.members.shaw.ca/chainsaw/SED/DfromBCdebounce.jpg

I think I just reinvented John Fields circuit (The circuit with the 2
one shots.)

Ok.....I'm going to look at your circuit.
As on..
http://s2.supload.com/free/Deglitch.JPG/view/


D from BC
 
J

John Larkin

Jan 1, 1970
0
---
It's not 'it's', it's 'its'.

So, you were asking for something frivolously, disregarding the
investment in time someone seriously interested in helping you would
have to expend in order to meet your ~10ns "requirement", when that
10ns spec was just there to make you look "cool" in your bosses'
eyes?
---


---
First you need to learn to walk.
---


---
Don't you mean that you can ask someone to do an ultra fast version
for you another day?

Anyway, here's the simulation I promised you, in LTSPICE:

Version 4
SHEET 1 1924 1060
WIRE -1040 -304 -1632 -304
WIRE -944 -256 -976 -256
WIRE -1040 -240 -1296 -240
WIRE -416 -224 -448 -224
WIRE -320 -224 -352 -224
WIRE -224 -224 -320 -224
WIRE -32 -224 -224 -224
WIRE 96 -224 32 -224
WIRE -1632 -208 -1632 -304
WIRE -1600 -208 -1632 -208
WIRE -1504 -208 -1536 -208
WIRE -1408 -208 -1504 -208
WIRE -1264 -208 -1408 -208
WIRE -320 -192 -320 -224
WIRE -32 -192 -112 -192
WIRE -224 -176 -224 -224
WIRE 208 -176 160 -176
WIRE -1504 -160 -1504 -208
WIRE -1152 -160 -1200 -160
WIRE -1088 -160 -1152 -160
WIRE -944 -160 -944 -256
WIRE -912 -160 -944 -160
WIRE 96 -160 64 -160
WIRE -1408 -144 -1408 -208
WIRE -1296 -144 -1296 -240
WIRE -1264 -144 -1296 -144
WIRE 208 -144 208 -176
WIRE -1152 -128 -1152 -160
WIRE 64 -128 64 -160
WIRE -1296 -112 -1296 -144
WIRE -800 -112 -848 -112
WIRE -912 -96 -944 -96
WIRE 64 -96 208 -144
WIRE -1296 -80 -1152 -128
WIRE 208 -80 64 -128
WIRE -1152 -64 -1296 -112
WIRE -320 -64 -320 -112
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FLAG -1632 928 0
FLAG -1408 256 0
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FLAG -320 928 0
SYMBOL res -1168 752 R90
WINDOW 0 -13 53 VBottom 0
WINDOW 3 39 54 VTop 0
SYMATTR InstName R6
SYMATTR Value 100k
SYMBOL cap -1312 784 R0
WINDOW 0 -38 31 Left 0
WINDOW 3 -56 56 Left 0
SYMATTR InstName C4
SYMATTR Value 1e-7
SYMBOL Digital\\or -1232 416 R0
WINDOW 0 3 107 Left 0
SYMATTR InstName A12
SYMATTR SpiceLine trise 1e-6 tfall 1e-6 vhigh 5v
SYMBOL Digital\\or -1232 704 M180
WINDOW 0 -1 114 Left 0
SYMATTR InstName A13
SYMATTR SpiceLine trise 1e-6 tfall 1e-6 vhigh 5v
SYMBOL voltage -1632 592 R0
WINDOW 0 -53 5 Left 0
WINDOW 3 -242 110 Invisible 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value PULSE(0 5 0 1E-6 1E-6 .1 .25)
SYMBOL cap -1536 432 R90
WINDOW 0 -30 32 VBottom 0
WINDOW 3 -28 35 VTop 0
SYMATTR InstName C5
SYMATTR Value 1e-7
SYMBOL res -1520 592 R0
SYMATTR InstName R7
SYMATTR Value 10k
SYMBOL diode -1392 672 R180
WINDOW 0 -39 33 Left 0
WINDOW 3 -75 -2 Left 0
SYMATTR InstName D2
SYMATTR Value 1N4148
SYMBOL Digital\\and -1008 320 R0
SYMATTR InstName A14
SYMATTR Value2 trise 1e-6 tfall 1e-6 vhigh 5v
SYMBOL voltage -1088 736 R0
WINDOW 0 28 15 Left 0
WINDOW 3 -242 110 Invisible 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V5
SYMATTR Value PULSE(0 5 0 1E-6 1E-6 .5e-3 1e-3)
SYMBOL Digital\\and -1008 736 M180
SYMATTR InstName A15
SYMATTR Value2 trise 1e-6 tfall 1e-6 vhigh 5v
SYMBOL Digital\\and -880 592 M180
SYMATTR InstName A16
SYMATTR Value2 trise 1e-6 tfall 1e-6 vhigh 5v
SYMBOL res -1168 96 R90
WINDOW 0 -12 56 VBottom 0
WINDOW 3 39 54 VTop 0
SYMATTR InstName R4
SYMATTR Value 100k
SYMBOL cap -1312 128 R0
WINDOW 0 -38 31 Left 0
WINDOW 3 -56 56 Left 0
SYMATTR InstName C1
SYMATTR Value 1e-7
SYMBOL cap -1536 -224 R90
WINDOW 0 -30 32 VBottom 0
WINDOW 3 -28 35 VTop 0
SYMATTR InstName C6
SYMATTR Value 1e-7
SYMBOL res -1520 -176 R0
SYMATTR InstName R5
SYMATTR Value 10k
SYMBOL diode -1424 -144 R0
SYMATTR InstName D3
SYMATTR Value 1N4148
SYMBOL Digital\\and -1008 -336 R0
SYMATTR InstName A7
SYMATTR Value2 trise 1e-6 tfall 1e-6 vhigh 5v
SYMBOL Digital\\and -1008 80 M180
SYMATTR InstName A8
SYMATTR Value2 trise 1e-6 tfall 1e-6 vhigh 5v
SYMBOL Digital\\and -880 -192 R0
SYMATTR InstName A18
SYMATTR Value2 trise 1e-6 tfall 1e-6 vhigh 5v
SYMBOL Digital\\and -1232 -240 R0
SYMATTR InstName A19
SYMATTR Value2 trise 1e-6 tfall 1e-6 vhigh 5v
SYMBOL Digital\\and -1232 48 M180
SYMATTR InstName A20
SYMATTR Value2 trise 1e-6 tfall 1e-6 vhigh 5v
SYMBOL voltage -1408 48 R0
WINDOW 0 28 15 Left 0
WINDOW 3 -242 110 Invisible 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V6
SYMATTR Value 5
SYMBOL Digital\\and -704 64 R0
SYMATTR InstName A5
SYMATTR Value2 trise 1e-6 tfall 1e-6 vhigh 5v
SYMBOL Digital\\and -704 400 M180
SYMATTR InstName A6
SYMATTR Value2 trise 1e-6 tfall 1e-6 vhigh 5v
SYMBOL Digital\\and -576 160 R0
SYMATTR InstName A9
SYMATTR Value2 trise 1e-6 tfall 1e-6 vhigh 5v
SYMBOL Digital\\inv -864 256 R270
SYMATTR InstName A10
SYMATTR Value2 trise 1e-6 tfall 1e-6 vhigh 5v
SYMBOL Digital\\and 352 240 R0
SYMATTR InstName A1
SYMATTR Value2 trise 1e-6 tfall 1e-6 vhigh 5v
SYMBOL Digital\\and 352 528 M180
SYMATTR InstName A4
SYMATTR Value2 trise 1e-6 tfall 1e-6 vhigh 5v
SYMBOL res 192 80 R90
WINDOW 0 -14 59 VBottom 0
WINDOW 3 39 54 VTop 0
SYMATTR InstName R9
SYMATTR Value 100k
SYMBOL cap 32 80 R90
WINDOW 0 0 32 VBottom 0
WINDOW 3 32 32 VTop 0
SYMATTR InstName C9
SYMATTR Value 2e-7
SYMBOL cap -352 -240 R90
WINDOW 0 -30 32 VBottom 0
WINDOW 3 -28 35 VTop 0
SYMATTR InstName C10
SYMATTR Value 1e-8
SYMBOL res -336 -208 R0
SYMATTR InstName R10
SYMATTR Value 10k
SYMBOL diode -240 -176 R0
SYMATTR InstName D5
SYMATTR Value 1N4148
SYMBOL Digital\\and 128 -256 R0
SYMATTR InstName A25
SYMATTR Value2 trise 1e-6 tfall 1e-6 vhigh 5v
SYMBOL Digital\\and 128 32 M180
SYMATTR InstName A26
SYMATTR Value2 trise 1e-6 tfall 1e-6 vhigh 5v
SYMBOL voltage -224 -32 R0
WINDOW 0 28 15 Left 0
WINDOW 3 -242 110 Invisible 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 5
SYMBOL res 192 832 R90
WINDOW 0 -15 59 VBottom 0
WINDOW 3 39 54 VTop 0
SYMATTR InstName R11
SYMATTR Value 100k
SYMBOL cap 32 832 R90
WINDOW 0 0 32 VBottom 0
WINDOW 3 32 32 VTop 0
SYMATTR InstName C11
SYMATTR Value 2e-7
SYMBOL Digital\\or 128 496 R0
WINDOW 0 3 107 Left 0
SYMATTR InstName A27
SYMATTR SpiceLine trise 1e-6 tfall 1e-6 vhigh 5v
SYMBOL Digital\\or 128 784 M180
WINDOW 0 -1 114 Left 0
SYMATTR InstName A28
SYMATTR SpiceLine trise 1e-6 tfall 1e-6 vhigh 5v
SYMBOL cap -352 512 R90
WINDOW 0 -30 32 VBottom 0
WINDOW 3 -28 35 VTop 0
SYMATTR InstName C12
SYMATTR Value 1e-8
SYMBOL res -336 640 R0
SYMATTR InstName R12
SYMATTR Value 10k
SYMBOL diode -208 720 R180
WINDOW 0 -39 33 Left 0
WINDOW 3 -75 -2 Left 0
SYMATTR InstName D6
SYMATTR Value 1N4148
SYMBOL Digital\\and 16 576 M180
SYMATTR InstName A29
SYMATTR Value2 trise 1e-6 tfall 1e-6 vhigh 5v
SYMBOL Digital\\or 0 -272 R0
WINDOW 0 3 107 Left 0
SYMATTR InstName A30
SYMATTR SpiceLine trise 1e-6 tfall 1e-6 vhigh 5v
TEXT -1608 896 Left 0 !.tran .5
TEXT -1344 -376 Left 0 ;SIGNAL GENERATOR
TEXT -184 -376 Left 0 ;DEBOUNCER
TEXT 512 448 Left 0 ;OUTPUT

The concept is there, and it works, so all you need to do is convert
the circuit to a TTL equivalency, if that's what you want to use,
and maybe use some diodes instead of gates to get the chip count
down.

You know how to do that, right?

Larkin's down to two chips, but he's got a lot of RFI going on since
every transition of the input signal generates spikes all through
his delay network and into the air.


Hairball.

John
 
J

John Larkin

Jan 1, 1970
0
Actually.. I've been neglecting to watch out for a freeze up problem.

I had another bandaid in mind..

The bandaid was adding 2 NAND gates and a SR to my cct on
http://www.members.shaw.ca/chainsaw/SED/DfromBCdebounce.jpg

That makes it even more complex, and adds new hazards.

It's extremely difficult, or more likely impossible, to prove that a
mess like this is safe. That's why asynchronous logic is seldom used
where it really matters.

A synchronous state machine can be proven to be correct. And it can
have hang states that are not a hazard because it can be proved that
they can never be entered. An async machine like this one will be
teased billions of times in its lifetime, and if it has a chance of
hanging, it probably will.
I think I just reinvented John Fields circuit (The circuit with the 2
one shots.)

You'll never prove that it's safe. It way too complex, and way to
slow, anyhow.
Ok.....I'm going to look at your circuit.
As on..
http://s2.supload.com/free/Deglitch.JPG/view/


D from BC

As has been pointed out a few times, it inverts. So take the output
from Qbar.

I'd still go for the lowpass-schmitt.


John
 
D

D from BC

Jan 1, 1970
0
On Sat, 03 Nov 2007 20:00:00 -0500, John Fields

[snip]
I could handle up to 100nS of edge delay but the circuit loses it's
'cool' appeal.

---
It's not 'it's', it's 'its'.

So, you were asking for something frivolously, disregarding the
investment in time someone seriously interested in helping you would
have to expend in order to meet your ~10ns "requirement", when that
10ns spec was just there to make you look "cool" in your bosses'
eyes?
---
Like driving a bicycle instead of a motorcycle. :(

---
First you need to learn to walk.
---
I can probably do a ultra fast version another day.

---
Don't you mean that you can ask someone to do an ultra fast version
for you another day?

Anyway, here's the simulation I promised you, in LTSPICE:
[snipped .asc file]

The concept is there, and it works, so all you need to do is convert
the circuit to a TTL equivalency, if that's what you want to use,
and maybe use some diodes instead of gates to get the chip count
down.

You know how to do that, right?

Larkin's down to two chips, but he's got a lot of RFI going on since
every transition of the input signal generates spikes all through
his delay network and into the air.

ok ...ok..
I guess it's (correct use of apostrophe) not cool to back off on a
spec after some time..
I should have included in the 1st post some dream specs, some lower
and upper specs.
I do have a real justified technical reason for needing minimal edge
to edge delay. Not just for sport...
And I do plan on building a debounce circuit this month.

I was trying to make this point....
If the circuit problem is too heavy then I'll settle for simpler
longer prop. time designs.
Those would be quicker to post and describe. Also, those designs can
be an inspiration to faster designs.

Yup... I've done some DTL circuits to reduce chips.

About your circuit.....

Holy frick batman! :O
What amount should I put on the check? :)

You did the generator too!

I cheated on that ... :p
http://www.members.shaw.ca/chainsaw/SED
2 sine generators and a comparator.

Huh...I didn't know the unused pins could be left open in LTSpice...I
guess I should read the whole manual someday...It was driving me nuts
to hook up all the unused inputs.

Heyy! This is a fun problem :)
I've got papers all over the floor from trying to figure this out on
my own..

k...I'm gonna take this circuit for a test drive... :)

Thanks. :)

More later...
D from BC
 
J

John Larkin

Jan 1, 1970
0
On Sat, 03 Nov 2007 19:45:01 -0700, John Larkin

[snip]
Hairball.

John

Oh come on... I think JFs (apostrophe used correctly?) has a logical
progression with low propagation in mind.

You can never prove that a thing like that works right. Which means
that it probably doesn't.
If I understand it correctly..

It's got edge extraction.
It's got 2 parallel paths per edge type.
And 2 timers to knock out the fuzz.

I'm guessing the required shopping list for this type of circuit is :

A means to detect the 1st positive edge.
A means to detect the 1st negative edge.
An ignore timer for the fuzz after the 1st positive edge.
An ignore timer for the fuzz after the 1st negative edge.

Hairball.

John
 
D

D from BC

Jan 1, 1970
0
This has got to be a classic signal clean up problem....

I need a circuit that triggers on edge A, then ignores about 0.1uS of
jitter then triggers on edge B and then ignores a following 0.1uS of
jitter.
I need a circuit that triggers on edge A, then ignores about 0.1uS of
jitter then triggers on edge B and then ignores a following 0.1uS of
jitter.
[where edge A is low-to-high and B is high-to-low]

So, use a nonretriggerable monostable with rising clock to
make a pulse at A, another with falling clock to make a pulse
at B, and Set/Reset a flop flop with those. Use the monostable A
output to gate (inhibit) the B trigger, and the B output to gate the
A trigger. As long as the monostable time
is set longer than the jitter window, you're golden.
Well, the trigger/output propogation delay has to be shorter than
the delay to first false transition...

For retriggerable monostables, the extra edges will stretch the
output pulse; if the stable time is guaranteed longer than the
monostable period, that's OK too.

The nonclassic solution is filtering followed by a Schmitt trigger.
That introduces phase delay, of course, and senses some average
over time rather than the initial edges.

It seems to be the trend.
I realized some of those monostable requirements when I tried to solve
the circuit.
Also, I suspect John Fields ascii circuit and posted LTspice file use
similar approaches.
One channel for the positive edge processing. A timing action.
One channel for the negative edge processing. A timing action.
Some cross resetting and final decoding..

The sequence is something like this.

Trigger on positive edge.
Let fuzz pass by.
Clear negative edge in preparation for 1st incoming negative edge.
Trigger on negative edge.
Let fuzz pass by.
Clear positive edge in preparation for incoming positive edge.

The pita part is attempting low prop delay for 1st pos edge and 1st
neg edge.
The SN74LV123A retrig MM has a tpd of 11nS@5V at the top of the
datasheet.
D from BC
 
D

D from BC

Jan 1, 1970
0
On Sat, 03 Nov 2007 19:45:01 -0700, John Larkin

[snip]
Hairball.

John

Oh come on... I think JFs (apostrophe used correctly?) has a logical
progression with low propagation in mind.

If I understand it correctly..

It's got edge extraction.
It's got 2 parallel paths per edge type.
And 2 timers to knock out the fuzz.

I'm guessing the required shopping list for this type of circuit is :

A means to detect the 1st positive edge.
A means to detect the 1st negative edge.
An ignore timer for the fuzz after the 1st positive edge.
An ignore timer for the fuzz after the 1st negative edge.


D from BC
 
D

D from BC

Jan 1, 1970
0
On Sat, 03 Nov 2007 18:32:05 -0800, D from BC
[snip]
Ok.....I'm going to look at your circuit.
As on..
http://s2.supload.com/free/Deglitch.JPG/view/


D from BC

As has been pointed out a few times, it inverts. So take the output
from Qbar.

I'd still go for the lowpass-schmitt.


John

I'm checking out how the Deglitch cct behaves when the frequency is
varied..

(I forgot to mention in my first post that the frequency can vary but
not the bounce period.)

The hairball circuits can react to varying pulse widths and have a
large operational BW.


D from BC
 
F

Fred Bloggs

Jan 1, 1970
0
D said:
This has got to be a classic signal clean up problem....

I need a circuit that triggers on edge A, then ignores about 0.1uS of
jitter then triggers on edge B and then ignores a following 0.1uS of
jitter.
I need a circuit that triggers on edge A, then ignores about 0.1uS of
jitter then triggers on edge B and then ignores a following 0.1uS of
jitter.

[where edge A is low-to-high and B is high-to-low]

So, use a nonretriggerable monostable with rising clock to
make a pulse at A, another with falling clock to make a pulse
at B, and Set/Reset a flop flop with those. Use the monostable A
output to gate (inhibit) the B trigger, and the B output to gate the
A trigger. As long as the monostable time
is set longer than the jitter window, you're golden.
Well, the trigger/output propogation delay has to be shorter than
the delay to first false transition...

For retriggerable monostables, the extra edges will stretch the
output pulse; if the stable time is guaranteed longer than the
monostable period, that's OK too.

The nonclassic solution is filtering followed by a Schmitt trigger.
That introduces phase delay, of course, and senses some average
over time rather than the initial edges.


It seems to be the trend.
I realized some of those monostable requirements when I tried to solve
the circuit.
Also, I suspect John Fields ascii circuit and posted LTspice file use
similar approaches.
One channel for the positive edge processing. A timing action.
One channel for the negative edge processing. A timing action.
Some cross resetting and final decoding..

The sequence is something like this.

Trigger on positive edge.
Let fuzz pass by.
Clear negative edge in preparation for 1st incoming negative edge.
Trigger on negative edge.
Let fuzz pass by.
Clear positive edge in preparation for incoming positive edge.

The pita part is attempting low prop delay for 1st pos edge and 1st
neg edge.
The SN74LV123A retrig MM has a tpd of 11nS@5V at the top of the
datasheet.
D from BC

It would be simpler to learn how to terminate your signals properly...
 
J

John Fields

Jan 1, 1970
0
On Sat, 03 Nov 2007 19:45:01 -0700, John Larkin

[snip]
Hairball.

John

Oh come on... I think JFs (apostrophe used correctly?)

---
Nope, apostrophes are used to form possessive of nouns, so it should
be "JF's". :)

http://owl.english.purdue.edu/handouts/grammar/g_apost.html
---
has a logical progression with low propagation in mind.

---
Yup. The positive edge processing is 5 gate delays from input to
output and the negative edge is 3. There's probably some
optimization that can be done, but I was just looking to prove the
validity of the concept.
---

If I understand it correctly..

It's got edge extraction.
It's got 2 parallel paths per edge type.
And 2 timers to knock out the fuzz.

I'm guessing the required shopping list for this type of circuit is :

A means to detect the 1st positive edge.
A means to detect the 1st negative edge.
An ignore timer for the fuzz after the 1st positive edge.
An ignore timer for the fuzz after the 1st negative edge.

---
Yes, but the timer is to keep the fuzz from firing the _other_
circuit once the first edge fires its own circuit.

Don't mind Larkin, he generally pooh-poohs everything that doesn't
come out of his shop. NIH, it's called. ;)
 
J

John Fields

Jan 1, 1970
0
On Sat, 03 Nov 2007 20:00:00 -0500, John Fields

[snip]
I could handle up to 100nS of edge delay but the circuit loses it's
'cool' appeal.

---
It's not 'it's', it's 'its'.

So, you were asking for something frivolously, disregarding the
investment in time someone seriously interested in helping you would
have to expend in order to meet your ~10ns "requirement", when that
10ns spec was just there to make you look "cool" in your bosses'
eyes?
---
Like driving a bicycle instead of a motorcycle. :(

---
First you need to learn to walk.
---
I can probably do a ultra fast version another day.

---
Don't you mean that you can ask someone to do an ultra fast version
for you another day?

Anyway, here's the simulation I promised you, in LTSPICE:
[snipped .asc file]

The concept is there, and it works, so all you need to do is convert
the circuit to a TTL equivalency, if that's what you want to use,
and maybe use some diodes instead of gates to get the chip count
down.

You know how to do that, right?

Larkin's down to two chips, but he's got a lot of RFI going on since
every transition of the input signal generates spikes all through
his delay network and into the air.

ok ...ok..
I guess it's (correct use of apostrophe) not cool to back off on a
spec after some time..
I should have included in the 1st post some dream specs, some lower
and upper specs.
I do have a real justified technical reason for needing minimal edge
to edge delay. Not just for sport...
And I do plan on building a debounce circuit this month.
 
Top