On Mon, 05 Nov 2007 10:17:23 -0600, John Fields
On Mon, 05 Nov 2007 07:05:08 -0800, John Larkin
On Mon, 05 Nov 2007 07:25:10 -0600, John Fields
On Sun, 04 Nov 2007 20:59:04 -0800, John Larkin
On Nov 4, 9:07 am, John Larkin
So, use a nonretriggerable monostable with rising clock
So what happens when a really fast spike fires both one-shots? What
happens when an edge comes in just about the time one or both
one-shots is timing out?
The problem, as stated, requires a circuit to operate in four
different phases:
Phase A: wait for a rising edge, go high when it does
Phase B: stay high, ignore edges for 'a while'
Phase C: wait for a falling edge, go low when it does
Phase D: stay low, ignore edges for 'a while'
So, something with two monostables or latches or whatever is required,
because the four states require two bits of state information. And
there are two time periods of some (presumably known) duration to
be part of the mix. It's required BY THE PROBLEM to have some
kind of one-shot to handle that timing, unless you can use higher-
speed
I posted a simple, fast circuit that works, is hazard-free, and has
few of the things that you say are "required by the problem."
Remember, the signal has states of its own, so the circuit doesn't
have to include all the states you enumerate.
Asynchronous logic can be scary, but this situation really calls for
it.
That's no reason to design hairballs.
---
Geez, if you want to see a hairball, take a look at your clock input
before the input signal gets stable!
It should be a roughly 10 ns positive pulse at every transition of the
input. The first such glitch clocks the r-c filtered data into the
dflop. Any additional glitches do the same thing. There's not even a
metastability hazard. This circuit is simple enough that a
humanly-possible analysis can demonstrate, with high confidence, that
it's safe.
You don't like it for personal reasons. That's a bad basis for
engineering.
---
On the contrary, I've used a similar circuit for years as a clean
transition detector:
.IN>---+----------A
. | EXOR Y-->OUT
. +--[R]-+---B
. |
. [C]
. |
. GND
The only thing I think that's wrong with your circuit is that at the
speed it's supposed to be used I think the EXOR chain is going to
generate a lot of hash as it follows the bouncing input.
I don't know what you mean by "hash." If you mean emi, well, any gate
that follows any signal generates "hash." Your circuits have lots of
logic transitions, too.