Maker Pro
Maker Pro

Design question on microcontroller and TIP122

KrisBlueNZ

Sadly passed away in 2015
Nov 28, 2011
8,393
Joined
Nov 28, 2011
Messages
8,393
Does the load, R2, need to connect to the negative rail?

As BobK said, if you're using an NPN, it's more usual to connect the load between the collector and the positive supply, and ground the emitter.

The way you've shown it uses the transistor as an emitter follower. In this configuration the transistor will drop around 0.7V.

If the load needs to connect to the negative supply, you should use a common emitter or common source stage with a PNP or P-channel MOSFET.

The connections for that configuration are: Transistor emitter, or MOSFET source, to positive supply rail. Transistor collector, or MOSFET drain, to positive side of load. Negative side of load to the 0V rail. Base or gate to the MCU output via a resistor. The transistor or MOSFET will conduct when the MCU output is LOW, not when it's HIGH. A pullup resistor between the base and emitter, or gate and source, is also a good idea.

So my recommendation would be a P-channel MOSFET, wired as just described. It should be a low-Vgs type, also called "logic level drive". These are more expensive than N-channel MOSFETs for the same level of performance, and there are less options available in through-hole. This one might be suitable: http://www.digikey.com/product-detail/en/NDP6020P/NDP6020P-ND/1055922. If you can deal with SMT, you have a lot more options. Also, if you don't need your load to be referenced to the 0V rail, you can use an N-channel MOSFET as I suggested earlier.

With the P-channel MOSFET arrangement, you also have to consider the voltage difference between the MCU's supply voltage and the load's supply voltage. The MCU's output will be 0V/+5V relative to the commoned 0V rail, but the MOSFET is controlled by the voltage on its gate relative to the source. So if the source voltage is not 5V then the MOSFET will not see 0V gate-source voltage when the MCU output is high.

Explain more about your project and the reasons behind the design decisions you have made so far.
 

dashy1981

Jun 19, 2013
83
Joined
Jun 19, 2013
Messages
83
ok... got it. I do not need my load to be connected to negative rails. And I'll go with load connected between collector and load.

Now I am plannng to get both TIP and NTD4906N for testing purpose.

Now the question is what should be the value of R1 and do i need any more resistors for current limiting ?
 

KrisBlueNZ

Sadly passed away in 2015
Nov 28, 2011
8,393
Joined
Nov 28, 2011
Messages
8,393
It's generally recommended that you put a small amount of resistance - something in the range of 10 ohms to 47 ohms - in series with a MOSFET gate. You may also want to put a resistor of, say, 10k between the MOSFET's gate and source, so that it turns off if the micro is not driving it (some micros set their I/O pins to high-impedance state during reset). You don't need any other resistors.

If your load is inductive, you should connect a diode across it in the reverse direction; that is, cathode to the positive supply rail, and anode to the MOSFET drain. This will provide a path for the "back EMF" current when the MOSFET turns OFF and the magnetic field in the load collapses.
 

dashy1981

Jun 19, 2013
83
Joined
Jun 19, 2013
Messages
83
I pondered over the suggestions and have one question. Should not always it be the case that Load be directly connected to ground and the VCC be switched by the switching device. I remember some experience hand telling me that I should connect GND first and then the positive lead to the load.

If that is the case than everyone should be using PNP or P channel devices exclusively for switching applications.
 

KrisBlueNZ

Sadly passed away in 2015
Nov 28, 2011
8,393
Joined
Nov 28, 2011
Messages
8,393
If the load is a circuit that needs to have its negative supply connected to the negative supply of the control circuit, then yes, you need to connect the negative rails together and switch the positive rail. This is a common requirement in battery switching applications in cellphones, for example, and there are P-channel MOSFETs optimised for those applications. PNP transistors can also be used if efficiency is not a concern.

It's also possible to use an N-channel MOSFET to interrupt a positive rail - the source needs to be connected to the output, and a higher-than-VCC voltage is needed for the gate. You can also use an NPN in emitter follower configuration, but this introduces significant voltage drop. As you say, a P-channel MOSFET is the simplest solution for switching the positive rail.

Switching the negative rail using an N-channel MOSFET is the simplest and most efficient arrangement, provided that the load is self-contained and doesn't need its negative supply to be permanently commoned to the negative supply of the circuit that feeds it. This is generally true when you refer to something as a "load" - we assume it's something like a motor, an LED, etc.

A quick look through this thread shows that you have not told us what your "load" is. Without this information, we do not know whether there's any need to switch the positive rail. This is why everyone here has assumed that your load is fully floating and will not mind having its negative rail switched.

If you want a good answer, provide us with some good information. In other words, describe your load.
 

dashy1981

Jun 19, 2013
83
Joined
Jun 19, 2013
Messages
83
Hi Kris... Thx for quick reply... my load is is a proprietry gsm modem... Max current: 800mA @4V. so I guess we have to treat it as a circuit(inductive as well ?).

I forgot to mention that on the suggestions in the thread I've got STP40NF12(I went searching for FQP30N06L but got this... seller suggested that they are interchangeable... but data sheet comparison showed that Vth is a bit higher for STP than for FQP ) and NDP6020P.

I'm going to experiment with these before actually using them in the circuit and to improve my understanding... any suggestions what circuit to try to understand the switching characteristics ?
Or I can follow below ckts.... by replacing motor with a resistor?
http://digital-diy.com/general-electronics/67-tip-logic-level-fets-p-channel.html
http://digital-diy.com/general-electronics/68-tip-logic-level-fets-n-channel.html
 

KrisBlueNZ

Sadly passed away in 2015
Nov 28, 2011
8,393
Joined
Nov 28, 2011
Messages
8,393
I would not be switching the power to a GSM modem. Every time you power it up, it will have to re-establish a connection with a cell site. This takes a while and wastes power. Also of course it won't be able to receive an incoming call while it's powered down, but I assume you don't need that. Still, I doubt it's appropriate to switch the power to it.

I think you should do another thing you should have done at the start of this thread: explain your application in detail. What are you trying to achieve? Details please.

Those pages you linked only tell part of the story. The Vgs(th) voltage is just the gate-source voltage at which the MOSFET _starts_ to conduct. If you want to achieve the specified Rds(on) figure, you need to provide more gate-source voltage than that. The STP40NF12 data sheet specifies Rds(on) (max) as 32 milliohms with Vgs=10V. The FQP30N06L data sheet species Rds(on) (max) as 35 milliohms with Vgs=10V, and 45 milliohms with Vgs=5V.

At gate voltages lower than those specified, the MOSFET is not saturated, and its maximum drain current is much lower than the specification summary at the top of the data sheet; more importantly, its Rds is much higher than shown in that specification summary.

The data sheet should have graphs for one or both of these relationships; bear in mind that the graphs show typical performance, not guaranteed performance. For guaranteed Rds(on) performance, look in the specification table under the Rds(on) specification; the associated Vgs voltage should be specified.

For standard MOSFETs, Rds(on) is usually specified with Vgs=10V. Some MOSFETs, called "logic level gate" or "low Vgs" MOSFETs, also have Rds(on) specified with lower Vgs voltagers - 4.5V is common, and some smaller MOSFETs that are designed for low-voltage switching in portable applications even include Rds(on) specifications for Vgs voltages as low as 1.8V!

You can certainly find N-channel and P-channel MOSFETs with Rds(on) resistances lower than 30 milliohms with Vgs voltages lower than 4.5V. Use Digikey's parametric filter system. To start with, only enable devices that are described as low-Vgs.

Anyway, first, please explain your application in detail and tell us why you want to switch power to the GSM modem.
 

dashy1981

Jun 19, 2013
83
Joined
Jun 19, 2013
Messages
83
Its basically regression test automation application. Certain set of test cases are run iteratively and after each iteration device(modem) needs to be reset. Each iteration may vary from 5 mins to 1.5 hrs. Logic to send various commands will be done using an 8051, serial port. Same 8051 will switch the device on/off once after each test case/iteration as programmed. hope it helps.
 

KrisBlueNZ

Sadly passed away in 2015
Nov 28, 2011
8,393
Joined
Nov 28, 2011
Messages
8,393
OK, fair enough.

In that case it's probably most appropriate to switch the positive supply to the modem. You should also make sure that any signal that feeds into the modem is at 0V before you power it down, otherwise it might (possibly) be damaged.

You can switch the supply rail using either an N-channel or P-channel MOSFET. A low-Vgs P-channel MOSFET is the simplest option. Connect its source to the VCC supply, and connect its drain to the VCC input of the modem. When the micro drives the MOSFET's gate low, the MOSFET will conduct and power up the modem.

Most of the suitable MOSFETs will be surface-mount devices. Here's one that looks like an excellent fit: http://www.digikey.com/product-detail/en/FDS4465/FDS4465CT-ND/965616

It's USD 1.21 in 1-up quantity, which is not an issue for a one-off project, and it claims an Rds(on) (max) of 10.5 milliohms with only 2.5V Vgs! It comes in an 8-pin SOIC package.

Edit: These devices are pretty sensitive. Connect a zener diode across the gate-source junction (cathode to source, anode to gate) - use something like 6.2V 0.5W. Observe anti-static precautions when handling the MOSFET. It wouldn't hurt to reverse-connect a diode across the load as well (cathode to drain, anode to 0V).
 
Last edited:

dashy1981

Jun 19, 2013
83
Joined
Jun 19, 2013
Messages
83
Thx Kris... but as I mentioned earlier I already have got NDP6020P with me, so will go with this one.

I've been reading through JFET,DMOS and EMOS from various sorces in the mean time. But all the equations/examples and circuits are for NMOS and PMOS ckts are told to be just the reverse of N MOS ckts.
This creates confusion for me and hopefully for many more like me. I've been trying to understand the example given in the link:
http://digital-diy.com/general-electronics/67-tip-logic-level-fets-p-channel.html

Initially I was assuming the MOS connected in the example shown to be in normal position(as generally shown for N Channel MOS) i.e. Drain upside and source downside. I was unable to digest this statement from the description in above link:

for example, your target device is being powered by 12 volts, and your logic high state from the micro controller is 5 volts, then the MOSFET will never turn off,
as Vgs will either be -12V or -7V (remember that this guide is designed for logic level MOSFET's)

Reason being I was assuming the ckt to be as shown as WrongUndrestanding.jpg(Note the MOS terminals), While the correct one should be Correct.jpg.... ??? Am I correct ?
With new understanding now, if I use Correct.jpg to analyze:
When ON:
VGG=5V, VDD=12V
VGS= VG -VS = 5 -(12) = -7V
When OFF:
VGG=0V, VDD=12V
VGS= VG -VS = 0 -(12) = -12V

Is this correct understanding ?
 

Attachments

  • WrongUndrestanding.JPG
    WrongUndrestanding.JPG
    20.4 KB · Views: 136
  • Correct.JPG
    Correct.JPG
    21.8 KB · Views: 128
Last edited by a moderator:

KrisBlueNZ

Sadly passed away in 2015
Nov 28, 2011
8,393
Joined
Nov 28, 2011
Messages
8,393
N and P polarities of MOSFETs, as well as for junction transistors, do cause confusion.

Your second diagram shows the general connection for a P-channel MOSFET. The first diagram is wrong. The last six lines of your post are wrong. I'll try to explain from the beginning.

First, remember that the electrode functions DO NOT CHANGE. In terms of how the device behaves, the source of an N-channel MOSFET corresponds to the source of a P-channel MOSFET. The source is always the terminal that connects to the middle bit with the arrow.

Second, remember that the polarities of all voltages, and the directions of all currents, are reversed for the P-channel MOSFET compared to the N-channel MOSFET.

Start with the basic operation of an N-channel MOSFET. The device is sensitive to the voltage between the gate and the source. If this voltage is zero, the MOSFET does not conduct any current through its drain-to-source path; it's like an open switch. As the gate-to-source voltage is increased (with the gate positive relative to the source), a voltage will be reached when the MOSFET starts to conduct current in its drain-to-source path. This is called Vgs(th) (gate-to-source threshold voltage). If the gate-source voltage is increased further, the MOSFET conducts more strongly; beyond a certain gate-source voltage the MOSFET conducts pretty much as hard as it can; this is called saturation. In this state, its drain-source path is equivalent to a very low-value resistor. The resistance of this path is called Rds(on). Because Rds(on) can be very low, MOSFETs can switch pretty heavy currents without much voltage drop between drain and source, and without much power (heat) dissipation. For an N-channel MOSFET, the current flows into the drain and out the source (for conventional current, which flows from positive to negative).

For a P-channel MOSFET, if the gate is brought NEGATIVE relative to the source, by a voltage greater than the threshold voltage (Vgs(th)), it will start to conduct current through its drain-to-source path. This current will flow into the source and out of the drain (for conventional current). If the gate is brought more negative relative to the source, the MOSFET will saturate.

P-channel MOSFETs are usually drawn upside-down from N-channel MOSFETs; this is because their source terminals are usually connected to the positive supply rail (the same way that N-channel MOSFETs often have their source terminals connected to the negative rail, which I'll call "0V"). But no matter the polarity of the device, it responds to a voltage on the gate relative to the source; it's the polarity of the voltage that differs.

In the case of a P-channel MOSFET with its source connected to the positive rail, pulling the gate towards the 0V (negative) rail applies gate bias to the device and makes it conduct. That's because it makes the gate negative with respect to the source. This is the same as applying a positive voltage to the gate of an N-channel MOSFET - it makes the MOSFET conduct. But with a P-channel MOSFET with its source connected to the positive supply rail, the drain becomes a switched positive output; when the device conducts, it energises this output with current from the positive supply rail. The load is then connected between the drain and 0V (negative supply rail).

The circuit shown on the digital-diy page uses an NPN transistor to pull the gate voltage down to 0V (making the gate 12V negative relative to the source) to turn the MOSFET ON. When the transistor is OFF, the 10k gate-to-source resistor pulls the gate voltage up to +12V so the gate-to-source voltage is zero and the MOSFET is OFF.

Regarding the choice of MOSFET: the one I suggested is a lot smaller and has much better performance, but the NDP6020P should be OK. With an Rds(on) of 0.07 ohms at -Vgs = 2.5V and a load current of 250 mA it will only drop 18 mV. 250 mA sounds pretty low for a GSM modem; they often draw more than 1A for brief periods of time while transmitting.
 
Last edited:

dashy1981

Jun 19, 2013
83
Joined
Jun 19, 2013
Messages
83
Thanks for explaining it so well..:). that was really wonderful... precise to the point. Instead of giving more equations i really liked your explaination in simple terms.

I have a few questions though:

1. You're right, during high Rf activity I expect current to go up drastically withing the limits you mentioned. So I have selected the part keeping that in mind(the one you suggested also I'll try when I get it).
Are you referring to some other datasheet or I am not reading it correctly. its here for reference:
http://www.fairchildsemi.com/ds/ND/NDB6020P.pdf

According to me with -Vgs=2.5V it can conduct upto -10A with Rds(on) in between 0.064 and 0.075 ohm. Am I missing something here ?

2. My micro has 5V logic which will drive the gate of MOSFET. Load voltage as I mentioned earlier is 4V. So when micro o/p is high then gate will be 1V positive relative to the source voltage of 4V, then MOSFET is non-conducting. When micro o/p is at 0V gate will be 4V negative wrt source, so the MOSFET will be conducting in this case, with Vgs = -4 V and Rds(on)=approx 0.041 to 0.05 Ohm and Id(on)= approx 24 A.
This means that the logic will be inverted ... Micro pin High => MOSFET/Load OFF and LOW => MOSFET/Load ON.

=> Is the understanding based on your earlier inputs and the data sheet in discussion correct ?
=> Also when gate is +ve wrt source is there any side affect ?
 

KrisBlueNZ

Sadly passed away in 2015
Nov 28, 2011
8,393
Joined
Nov 28, 2011
Messages
8,393
According to me with -Vgs=2.5V it can conduct upto -10A with Rds(on) in between 0.064 and 0.075 ohm. Am I missing something here?
No, that's right. The issue is the amount of voltage it will drop. If your peak current is say 1.5A and Rds(on) is 0.070 ohms, the voltage drop (calculated using Ohm's Law: V = I R) is 0.135 volts. This probably isn't a problem, but you could definitely improve on that voltage drop. You will already be seeing a voltage drop if the circuit is powered from a battery.

2. My micro has 5V logic which will drive the gate of MOSFET. Load voltage as I mentioned earlier is 4V. So when micro o/p is high then gate will be 1V positive relative to the source voltage of 4V, then MOSFET is non-conducting. When micro o/p is at 0V gate will be 4V negative wrt source, so the MOSFET will be conducting in this case, with Vgs = -4 V and Rds(on)=approx 0.041 to 0.05 Ohm and Id(on)= approx 24 A.
This means that the logic will be inverted ... Micro pin High => MOSFET/Load OFF and LOW => MOSFET/Load ON.
That's right, except that the 24A figure is just the maximum allowable drain current according to the MOSFET's specification.

Also, where do you get your 0.041~0.05 ohm ON resistance at -Vgs = 4.0V? The data sheet doesn't specify a maximum Rds(on) at -Vgs = 4.0V and there is no typical characteristics graph. Did you use the first graph that shows Vds vs. Id with traces for various -Vgs values? Also does your 4V supply come from a battery? If so, you need to calculate Rds(on) with the lowest possible voltage.

Also when gate is +ve wrt source is there any side affect ?
No. The only restriction on the gate-source voltage is the Vgs limit on the data sheet, which is typically ±15V. For this device, it's only ±8V. That just means that the gate voltage must not be brought more than 8V away from the source in either direction (positive or negative).

It's common to connect a zener diode across the gate-source terminals of a MOSFET to protect the gate insulation layer from overvoltage. The zener is connected so that it clamps the reverse gate bias to 0.7V (the zener is forward-biased, i.e. its anode is positive relative to its cathode, when the gate is reverse-biased) and it clamps the forward gate bias to the zener voltage.

This corresponds to the following connections:
N-channel MOSFET: zener cathode to gate; zener anode to source;
P-channel MOSFET: zener anode to gate; zener cathode to source.

You can do this, but because you need to drive the gate up to 1V positive relative to the source, you need to connect another diode in series with the zener, to increase the forward voltage from 0.7V to 1.4V, and you need another diode across that diode to conduct in the other direction. So the circuit (for a P-channel MOSFET) would be:

Code:
source ----------|<|------------|<|--------- gate
           |             |    1N5231B
            -----|>|-----
               2x 1N914

I should add that there is significant capacitance between the gate and the source. If you need the MOSFET to switch very quickly, you need to drive the gate with significant current to charge or discharge this capacitance. This won't be needed here, because the switching frequency is very low.

Finally, it's common to put a resistor between a low-current output (such as your microcontroller) and the MOSFET gate, to limit the current out of the microcontroller when it charges or discharges the gate capacitance. Calculate the resistance using Ohm's Law with the maximum allowed load current on the micro's pin and the micro's supply voltage. For example if the maximum output current is 20 mA and the supply voltage is 5V, R = V / I = 5 / 0.02 = 250 ohms; use 270 ohms.
 

dashy1981

Jun 19, 2013
83
Joined
Jun 19, 2013
Messages
83
No, that's right. The issue is the amount of voltage it will drop. If your peak current is say 1.5A and Rds(on) is 0.070 ohms, the voltage drop (calculated using Ohm's Law: V = I R) is 0.135 volts. This probably isn't a problem, but you could definitely improve on that voltage drop. You will already be seeing a voltage drop if the circuit is powered from a battery.
Thanks for clarifying... I was neglecting it, in my calculations. But my device is can operate from 3.8 to 4.2 V, so it should not matter much. Although will try to minimize it. Although I could not understand the last line. Why should it matter whether its a battery or a power supply ? However my micro is on 5V,1A adapter while load is on a variable good quality Power Supply.

Also, where do you get your 0.041~0.05 ohm ON resistance at -Vgs = 4.0V? The data sheet doesn't specify a maximum Rds(on) at -Vgs = 4.0V and there is no typical characteristics graph. Did you use the first graph that shows Vds vs. Id with traces for various -Vgs values? Also does your 4V supply come from a battery? If so, you need to calculate Rds(on) with the lowest possible voltage.
Sorry... i misread it. It was mentionend for VGS=-4.5 V. But looking at "Figure 2. On-Resistance Variation with Gate Voltage and Drain Current" can we approx it to 1.05 Ohm @ -4V, 1A ?? Again I could not get the reason for the last line... why in case of battery do i ned to calculate Rds(on) with lowest possible voltage ?

You can do this, but because you need to drive the gate up to 1V positive relative to the source, you need to connect another diode in series with the zener, to increase the forward voltage from 0.7V to 1.4V, and you need another diode across that diode to conduct in the other direction. So the circuit (for a P-channel MOSFET) would be:
Code:
source ----------|<|------------|<|--------- gate
           |             |    1N5231B
            -----|>|-----
               2x 1N914
To hone my understanding I'll divide it into two extreme conditions. VGG=5V and VDD=4V in normal scenario. please correct me if i am wrong.:D
1. When VGG=20V(by some means/fault in ckt), VDD=4V ==> VGS will exceed +-8V limit.
In that case gate is +ve wrt source by 16V, so one of 1N914 and zener 1N5231B will be FWD biased. Thus GS junction is protected.

2. When VGG=5V and VDD=20V by some means ==> Gate 15V -ve wrt source. VGS limit exceeded again.
In that case one of 1N914 is fWD biased and zener 1N5231B will act as closed switch after reverse voltage reaches Vz(In this case 5.1V ??) is reached.

All other suggestions understood and taken care of.
 

KrisBlueNZ

Sadly passed away in 2015
Nov 28, 2011
8,393
Joined
Nov 28, 2011
Messages
8,393
Although I could not understand the last line. Why should it matter whether its a battery or a power supply?
Because a battery's terminal voltage drops as it discharges, and will also drop temporarily during times of heavy load because of the battery's internal resistance. Assuming you want the circuit to work up until the point where the battery is practically flat, you need to design it using the minimum battery voltage, under load.

Sorry... i misread it. It was mentionend for VGS=-4.5 V. But looking at "Figure 2. On-Resistance Variation with Gate Voltage and Drain Current" can we approx it to 1.05 Ohm @ -4V, 1A??
The vertical axis on Figure 2 is not resistance in ohms; it's normalised resistance, where 1 represents the "normal" or standard resistance.

I'm not entirely sure how you're supposed to figure out what resistance this "normal" value of 1.0 corresponds to. If it wasn't for that fact, that would be the best graph to use.

Looking at that graph more closely, there is only one trace that actually crosses the 1.0 line; it's for -Vgs = 4.5V and Id ~ 13A. This may correspond to the Rds(on) line in the "ON CHARACTERISTICS" section of the specification table, which specifies test conditions of -Vgs = 4.5V and Id = 12A, at 25 degrees Celsius. In that case, 1.0 on the graph corresponds to an ON-resistance of typically 0.041 ohms, maximum 0.050 ohms (although using the maximum with the graph gives a misleading result because the graph is only typical, not worst-case).

If that's true, then with -Vgs = 4.0V and a drain current of a few amps or less, the relevant trace is only slightly above 1.0 - I estimate about 1.04, so the typical ON-resistance would be about 0.043 ohms. With -Vgs = 3.5V, typical ON-resistance would be about 0.046 ohms. None of these are maximum figures, and the maximum can't be calculated using that graph.

To hone my understanding I'll divide it into two extreme conditions. VGG=5V and VDD=4V in normal scenario. please correct me if i am wrong.:D
1. When VGG=20V(by some means/fault in ckt), VDD=4V ==> VGS will exceed +-8V limit.
In that case gate is +ve wrt source by 16V, so one of 1N914 and zener 1N5231B will be FWD biased. Thus GS junction is protected.
2. When VGG=5V and VDD=20V by some means ==> Gate 15V -ve wrt source. VGS limit exceeded again.
In that case one of 1N914 is fWD biased and zener 1N5231B will act as closed switch after reverse voltage reaches Vz(In this case 5.1V ??) is reached.
Yes, that's the idea. You've got the forward and reverse biasing part right. The action of the diodes is to clamp the gate-to-source voltage, i.e. to prevent it from exceeding those limits of about +1.5V and -5.8V.

The best reason for them is that if you put them right next to the MOSFET, the MOSFET is protected against anything that might happen at the other parts of the tracks (especially the gate track) (within reason - the diodes can't protect against high currents). For example if your micro is socketed, when you remove it, the gate line will float. The diodes are just a safety feature to protect the MOSFET gate, which is sensitive. This is also why you need to use anti-static precautions when handling MOSFETs until they have been installed and connected to a (relatively) low-impedance circuit point.

One more thing. You should put a resistor (10 kilohms for example) between the gate and source of the MOSFET as well. This will ensure that the MOSFET turns OFF when the gate signal is not being driven, which will happen while the micro is being reset, while its digital I/O pins are all in a high-impedance state. Actually it's best to connect it at the micro side of the 270 ohm gate resistor, otherwise you lose a bit of gate-source voltage because of the voltage divider effect of the two resistors.
 

KrisBlueNZ

Sadly passed away in 2015
Nov 28, 2011
8,393
Joined
Nov 28, 2011
Messages
8,393
I just noticed that you're using an 8051 to drive the MOSFET gate. The 8051 port architecture is unusual; it's called "quasi-bidirectional" and the pin pulls up only weakly. (It pulls down strongly.) This means there's no problem with clamping the gate voltage to one diode drop above 4V, so you don't need the two 1N914 diodes in the diagram I drew - you can just connect the zener straight across the gate-source of the MOSFET. When the micro's output pin goes high, it will be clamped to about 4.7V but this is not a problem with a quasi-bidirectional output.

Also make sure you have the pullup resistor (10k for example) between the microcontroller's output and a positive rail; it could be +5V or +4V, it doesn't really matter which. This will be needed to turn the MOSFET OFF reasonably quickly when the microcontroller output goes high, because the microcontroller does not pull its output high strongly, only weakly.
 

dashy1981

Jun 19, 2013
83
Joined
Jun 19, 2013
Messages
83
As I had mentioned in previous post, before trying out the final ckt, I am going to experiment a bit with these cute devices.
I have got two working ckts with Nmos and PMOS both. I'll discuss PMOS here so as not to divert the thread.

I've used a voltage divider to check the turn on/off characteristics of device. I only had one 220 Ohm POT(1/2 Watt), so decided R1=750 Ohm,
so that I can have voltage variance of 0 to 9V across POT. My load is a 12V motor, but based on the power adapters available right now with me, I'm driving it with 6V. The ckt is as attached. its just used to experiment so no zener present, but diode across motor is used.

I set Pot so that Voltage across it is 7V. Below is what I was expecting:
When switch is open, which means gate is 6V -ve wrt source ==> MOS should be ON.
Once switch is closed which means gate is 1V +ve wrt source ==> MOS should be off.

But I had strange observation: whether switch is ON/OFF MOS is off. But if I connect Multimeter to measure voltage drop between Gate and GND terminal
ckt behaves as expected.

Then only I realized that my gate is floating, when switch is open !!!! Connecting Multimeter might be working as a weak pull down resistor ????
So once multimeter is kept connecting across the Gate and GND Gate is no more floating and hence ckt works as expected...

Is this right understanding ?
 

Attachments

  • PMOs_testCkt.JPG
    PMOs_testCkt.JPG
    58.2 KB · Views: 172

KrisBlueNZ

Sadly passed away in 2015
Nov 28, 2011
8,393
Joined
Nov 28, 2011
Messages
8,393
Yes, your explanation sounds likely. I'm not sure about your voltage calculations.

I don't think you need to make up a test circuit; the arrangement is simple enough.
 

dashy1981

Jun 19, 2013
83
Joined
Jun 19, 2013
Messages
83
I just noticed that you're using an 8051 to drive the MOSFET gate. The 8051 port architecture is unusual; it's called "quasi-bidirectional" and the pin pulls up only weakly. (It pulls down strongly.) This means there's no problem with clamping the gate voltage to one diode drop above 4V, so you don't need the two 1N914 diodes in the diagram I drew - you can just connect the zener straight across the gate-source of the MOSFET. When the micro's output pin goes high, it will be clamped to about 4.7V but this is not a problem with a quasi-bidirectional output.

Also make sure you have the pullup resistor (10k for example) between the microcontroller's output and a positive rail; it could be +5V or +4V, it doesn't really matter which. This will be needed to turn the MOSFET OFF reasonably quickly when the microcontroller output goes high, because the microcontroller does not pull its output high strongly, only weakly.

You stumped me completely here... from datasheet:

The Port 1 is an 8-bit bi-directional I/O port. Port pins P1.2 to P1.7 provide internal pull-ups. P1.0 and P1.1 require external pull-ups. Port 3 pins P3.0 to P3.5, P3.7 are seven bi-directional I/O pins with internal pull-ups.

1. Although I use pull up of 10K always with port... as recommened by various HW engineers, but I must admit without much understanding. will be great if you could explain a bit more about weak pull up ans strong pull down... what do they mean practically.
2. If I put only zener across Gate and Source, then when Micro o/p is high, would it not FWD bias zener and make VGS=0.7V. While in my case I want atleast 1V.

Have a feeling that this thread is becoming quite a tutorial on practical electronics :D
 

KrisBlueNZ

Sadly passed away in 2015
Nov 28, 2011
8,393
Joined
Nov 28, 2011
Messages
8,393
Yes. The 8051's port architecture (on all ports except port 0) is called quasi-bidirectional. The digital I/O ports on most microcontrollers have a readable input register, a read/write output register, and a read/write data direction register (DDR) (on PICs, it's called the tri-state register, I think), with the data direction register explicitly setting the operating mode of each port line as either input or output, but the 8051 has only one addressable location for each port. That location addresses a read-only input register (when a read is performed on the location) or a write-only output register (on a write to that location). There is no data direction register.

Each port pin is directly readable through the corresponding bit in the input register, and each bit in the output register controls a strong pulldown / weak pullup arrangement on the port pin.

If the bit in the output register is set to 0 by firmware, using the CLR bit instruction, this enables a strong pulldown inside the 8051, which actively pulls the port pin down to the 0V (VSS) rail (low). When 8051 port pins are used as outputs, they are usually designated as active-low signals, i.e. signals that are in the active state when they are low; writing a 0 to the output port bit causes the 8051 to assert the output low (0V), which is the active state for the signal, and enables the connected device or circuit. Writing 1 to the port (SETB bit) causes the pin to be pulled high (inactive).

If the bit in the output register is set to 1 by firmware (using SETB bit), the strong pulldown is turned off, and a weak pullup is enabled. This weak pullup is like a weak spring that pulls the port pin towards VDD (5V in your case). It is so weak that it is easily overridden by external circuitry, which can easily drive the pin low. This low state will then be read by firmware on the read-only input register, using the JB and JNB instructions, which test a specific bit and jump to the branch target location if the bit is set (JB instruction) or clear (JNB instruction).

This arrangement can work quite well when the surrounding circuit is designed with active-low signals. For example, pushbuttons and switches can just be connected between the port pins and the 0V rail; firmware writes 1 to the output register and the weak pullup pulls the pin high (so it reads 1 on the input register) unless the switch or pushbutton is closed, in which case the pin is pulled low and reads 0 on the input register.

Here's a summary of how the 8051's bit manipulation instructions can be used to control and read the state of quasi-bidirectional port pins.

Drive a port bit high when wired as an output: SETB bit (weak pullup pulls port pin high weakly)
Drive a port bit low when wired as an output: CLR bit (strong pulldown pulls port pin low strongly)
Set a port bit to input mode: SETB bit (port has a weak pullup and can be pulled low externally)
Branch if input port bit is high: JB relative
Branch if input port bit is low: JNB relative.

These quasi-bidirectional ports also have a feature whereby a stong pullup is very briefly enabled when the output register is set to 1. This helps the pin pull high when there is a capacitive load on it. After a very short time (measured in clock cycles; I'm not sure of the details), the strong pullup turns off and only the weak pullup remains.

Port 0 is slightly different: it doesn't have a weak pullup at all. They have two states: strong pulldown, or float. The port 0 pins need some external path to VDD - either an external pullup resistor (or any kind of current source), or, for pins that are used as inputs, a normal logic-level drive that pulls both high and low.

Port 0 pins are what's known as open-drain ports; that is, there's a MOSFET inside the 8051 with its source connected to VSS (0V) and its drain connected to the port pin, but the drain is "open" in that there's nothing connected between it and the VDD rail. If the MOSFET is turned ON (by a 0 written to the port output register), it can pull its drain low strongly, but there's nothing inside the 8051 to pull the drain high; that must be provided externally.

The pins on port 1, 2 etc are also open-drain but with the addition of the weak pullup circuitry.

If you put just the zener from the gate to the source of your P-channel MOSFET, which is switching your +4V rail, when the 8051's output is high, yes, the zener will be forward-biased and it will clamp the gate voltage to about 4.7V. From the MOSFET's point of view, -Vgs will be -0.7V. This will not damage the MOSFET; when -Vgs is less than -Vgs(th) the MOSFET is OFF, so a little bit of reverse gate voltage just turns it OFF a bit more (i.e. doesn't do anything). You do not need -Vgs to be -1V; as long as it's 0V or less, the MOSFET is guaranteed to be OFF.

The zener will prevent the 8051's pin from pulling all the way to VDD (+5V) but since the pullup circuit in the 8051 is only weak, only a small amount of current will flow, and this is not a problem at all.

The reason for the pullup resistor is to ensure that the MOSFET turns OFF cleanly, and not too slowly, when firmware writes 1 to the output register bit. If you were to rely on the internal weak pullup in the 8051, the gate would not pull high very firmly, and the gate-source capacitance in the MOSFET would slow down the transition. You want the MOSFET to switch cleanly and not too slowly, because it dissipates power during the changes from OFF to ON and from ON to OFF.

So I suggest a resistor of around 10k from the 8051 pin to the MOSFET's source (the +4V rail), a 270 ohm resistor from the 8051 pin to the MOSFET's gate, and a 5.1V (or 5.6V or 6.2V if you like) 0.5W zener diode with its anode to the gate and cathode to the source.
 
Top