# Digital Counters Count Sample External Frequency Wrongly

#### Micro-e

May 27, 2021
6
Please see the attached schematic. I am experimenting with a circuit for sampling an external frequency. The counters do not always count correctly. At first I suspected the breadboard and I replaced it with no success.
I would like to know if anybody understands what mistake I have in my circuit which results in wrong count. It seems to me the only reason could be timing. I also experimented with timbases of 8, 16, 64, 128, 256 and 512 HZ. But it looks like that a timebase with lower frequency produces less sever errors for counting the pulses.

The update pulse (UPD) and reset pulse (RST) are derived from AND gates and inverters fed by the outputs Qk, Qj and Qi of a 4040 counter which divides a 32768 HZ frequency obtained from a crystal controlled timebase. All ICs are bypassed by a capacitor from their VCC to ground.
The 163 counters count during half cycle of the 32 HZ timebase or during 1/64 seconds. The output of the counters is fed to a 373 latch. If, for example, the counter counts the 1 HZ during 1/64 sec, then the output of the latch should be 1000 / 64 = 15.6 as either 15 or 16.
The problem is that the count, which I verify by an oscilloscope at the output of the latch, is not correct and the problem could be metastability which was not resolved with two D flip-flops is series.
Here are some examples:
Clock = I HZ, output of the latch is 00011111 which is double of 00001000.
Clock = 2 KHZ, output is 00111111 which corresponds to 4 KHZ.
Clock = 2.4 KHZ, output is 00100111 which corresponds to 2.96 KHZ.
Clock = 3 KHZ, output is 00101111 which corresponds to 3.008 KHZ and is acceptable.
Clock = 4 KHZ, output is 00111111 which corresponds to 4.032 KHZ .
Clock = 4.6 KHZ, output is 01001010 which corresponds to 4.736 KHZ .
Clock = 5 KHZ, output is 01001111 which corresponds to 5.056 KHZ .
Clock = 8 KHZ, output is 01111111 which corresponds to 8.128 KHZ .
Clock = 9 KHZ, output is 10001111 which corresponds to 9.344 KHZ .
Clock = 10 KHZ, output is 10011010 which corresponds to 9.856 KHZ .
I am particularly concerned with when the error at the output of latch is more than 65 HZ.
I use pulse generator of my oscilloscope for generating the input clock frequency to the 163 counters.

When I use output of Qf (1 KHZ) of the 4040 of the timebase generator as input clock from the 163 counters and the same two AND gates and inverters to generate the update and reset pulses, I do get the correct count at the output of the latch. This reveals the timing issue for getting the right count of an external frequency. So, how can we correctly read (sample) an external clock frequency that comes from a source other than the 4040?

The actual connection of counters and latch is as shown in the original schematics. I included the timebase generator, the gates, part numbers, and a picture of the oscilloscope. I had taken the pictures when I was testing 16 HZ timebase with similar results. I had two probes but unfortunately one of my probes is now defective so I could not show the pulses on one screen when I took the new picture with 32 HZ. I hope this can help. When I used a low pass filter of 100 KHZ all outputs of the latch went high. So I eliminated the filter from the circuit.

Could someone who is well experienced with frequency sampling tell me why the count is wrong specially when the count is double?

I appreciate your response and thank you.

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#### Harald Kapp

##### Moderator
Moderator
Nov 17, 2011
12,720
It looks like the two counters are connected in the wrong order. In your circuit the lower counter is the fast one but is connected to output bits Q5...Q8 whereas the upper counter is the slower one but connected to output bits Q0...Q4. See e.g. here how to connect the counters correctly:

But this can be helped by simply reordering the output bits. This is not related to your issue.

Next: do you realize that RESET (CLR) in these counters is synchronous? Setting CLR low alone will not reset the counters. You need to apply a clock pulse while CLR is low (datasheet)

You cannot guarantee this scenario with your circuit, thus the counter may effectively not start from zero, giving you random readings. This may be the cause why you see correct readings when connecting the count input to the 4040 as you will then have a clock pulse while RESET (CLR) is low.

#### Micro-e

May 27, 2021
6
It looks like the two counters are connected in the wrong order. In your circuit the lower counter is the fast one but is connected to output bits Q5...Q8 whereas the upper counter is the slower one but connected to output bits Q0...Q4. See e.g. here how to connect the counters correctly:
View attachment 51908
But this can be helped by simply reordering the output bits. This is not related to your issue.

Next: do you realize that RESET (CLR) in these counters is synchronous? Setting CLR low alone will not reset the counters. You need to apply a clock pulse while CLR is low (datasheet)
View attachment 51909
You cannot guarantee this scenario with your circuit, thus the counter may effectively not start from zero, giving you random readings. This may be the cause why you see correct readings when connecting the count input to the 4040 as you will then have a clock pulse while RESET (CLR) is low.

Thank you very much for your good response.

I connected the ENT and ENP inputs according to the attachment you sent to me. Also, because creating the reset pulse while a clock pulse is present seemed to need extra steps and I was not sure how to do it, I decided to call the reset pulse Load pulse and feed it to pin 9 of both counters to load all grounded inputs A, B, C and D of the counters with zeros instead of resetting the counters. In order for this method to work, I had to provide a logic high for the input A so that counters start counting from 1. Otherwise, the first counter would not load the zeros at its inputs. So, I ended up with Update, Load binary 00000001 and count again. As a result, the count is always 1 higher than the best count the counters can provide.

If instead of connecting the input A to logic high I ground the pin 9 of the counters by a resistor (while the pin 9 s are fed by the Load pulse), it has the same effect as counting from 00000001.

Now, do you know how could I avoid adding 1 to the count?

Thank you

#### Harald Kapp

##### Moderator
Moderator
Nov 17, 2011
12,720
In order for this method to work, I had to provide a logic high for the input A so that counters start counting from 1. Otherwise, the first counter would not load the zeros at its inputs.
Doesn't sound logical. Why would the counter refuse to load 0000 but load 0001?
Show a circuit diagram of what you did.

#### Micro-e

May 27, 2021
6
1- Attached is an image of the new connections. Do you see anything wrong with this circuit which is supposed to load zeros to start counting from zero in each timebase cycle?

2- I did not mention this before but the count is always 1 to 3 more than what it should be. For example, when input frequency is 4.61 KHz, the count is 01001011 instead of 01001000 (the right count would be 4610 Hz / 64 = 01001000 (2)).

3- The purpose for all that counting is addition of binary numbers represented by frequencies. I wanted to keep this question for later but perhaps it is good to mention it now with the hope that you have the patience to think about it for a good response. I have two sets of the cascaded 74HC163 counters and their associated registers to count two input frequencies and then feed the 8 bits output of each of the counters to a 74HC283 for adding the two counted binary numbers. However, the sum total is not exact. For example, if the first counter is fed with 876 Hz (and counts 00001111), and the second counter with 500 Hz (and counts 00001001), the sum is 00011111 instead of 00011000.

As you can see from the timing diagram, before the update pulse is generated, there is about 4 milli-sec time for all propagation delays to settle down while the update and load pulses are generated during the time that the counter is idle. Thus, I expect the output of the registers to be correctly settled down by after the update pulse is generated and before the load pulse is generated. And with the settled output of the registers, I expect the addition to happen correctly. Do I still need another register at the output of the adder to capture the right sum? If so why? In that case I have to use so many more ICs than expected.

NOTE: When I fed the two counters by for example Qe end Qf outputs of the 4040, I could capture the right sum even without the registers.

I would greatly appreciate if you could tell me what mistake am I making in the circuit.
Thank you

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#### Harald Kapp

##### Moderator
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Nov 17, 2011
12,720
You still have the upper nubble and the lower nibble of the 8 bit counter made from 2 × 74HC163 swapped. Compare your image with the one in my post #2.

#### Micro-e

May 27, 2021
6
Hi:

I think I was focusing more on the hardware I was working on and I did not realize my mistake on the schematics. I corrected the schematics and I attached them to this post to show the correct sequence of the lower and higher nibbles of the two counters. In my hardware setup, the connections of the lower nibble of the counters were not swapped from the beginning but I am sorry that I showed them wrongly in the schematics. What made a change for the counting was the correction you suggested by the attachment to your post #2 to the ENP and ENT of the counters.

So, my problems remain as I explained in my post #5. Could you see the actual mistake(s) with regards to what I explained in my post #5?

Thank you

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#### Harald Kapp

##### Moderator
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Nov 17, 2011
12,720
I see no difference between the images in post #5 and post #7. Both are wrong.

#### Micro-e

May 27, 2021
6
I changed the order of the pin numbers on the 373 register to show the output of each counter is directed to the register in right sequence. If that is not the correction, can you tell me which pin numbers of the counters of my schematics are you referring to? I see my connections the same as you suggested in your post #2. And sorry I was supposed to explain the changes I made but I was a bit fast to reply. My problem is as explained in my post #5 and the schematic in imageForum3. Thanks

Last edited:

#### Harald Kapp

##### Moderator
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Nov 17, 2011
12,720
I'm not talking abut the registers. The counters (HC163) are connected in the wrong order. See post #2.
Unless I miss an important fact, that is.

#### Micro-e

May 27, 2021
6
I'm not talking abut the registers. The counters (HC163) are connected in the wrong order. See post #2.
Unless I miss an important fact, that is.
Can you please be more specific with PIN numbers because I am not able to see where is my mistake.

#### Harald Kapp

##### Moderator
Moderator
Nov 17, 2011
12,720
Pin numbers won't help as both counters use the same pin numbers.
In your diagram the lower counter counts the lower nibble (Q0...Q3), the upper counter counts the upper nibble (Q4...Q7):

This is because the RCO of the lower counter goes to the ENP and ENT of the upper counter (red line). But the output of the 74HC373 uses the output of the lower nibble counter as the higher nibble and vice versa.
Compare this to the circuit I posted, I'll repeat it here annotated:

You clearly see Q0...Q3 coming from the counter for the lower nibble, the one where RCO is used as output as well as Q4...Q7 coming from the counter for the upper nibble, the one where RCO from the previous counter is used as input.

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