C
colin
- Jan 1, 1970
- 0
Hi,
I need a circuit to divide a <50mhz digital signal by 25/16.
ie. i need to lose 9 out of every 25 pulses.
Is there a simple/standard way to do this ?
Ive come up with a few ideas that use quite a lot of logic,
such as a divide the input by 25 with 1-25 decoder wich then swallows a
pulse at the apropriate count.
or divide by 16 on the output wich swallows a pulse every other count and
also at terminal count.
but it runs into trouble becuse it swallows its own clock pulses and doesnt
advance.
or invert the clock input to a flip flop with an xor from its output, wich
gives a nice looking pulse train
but needs a few more pulses taken out.
Its to go after a 3ghz divide by 64 prescaler so the combined divide is 100.
Colin =^.^=
I need a circuit to divide a <50mhz digital signal by 25/16.
ie. i need to lose 9 out of every 25 pulses.
Is there a simple/standard way to do this ?
Ive come up with a few ideas that use quite a lot of logic,
such as a divide the input by 25 with 1-25 decoder wich then swallows a
pulse at the apropriate count.
or divide by 16 on the output wich swallows a pulse every other count and
also at terminal count.
but it runs into trouble becuse it swallows its own clock pulses and doesnt
advance.
or invert the clock input to a flip flop with an xor from its output, wich
gives a nice looking pulse train
but needs a few more pulses taken out.
Its to go after a 3ghz divide by 64 prescaler so the combined divide is 100.
Colin =^.^=