Does clock pulsewidth affect the 4017 ?

[AFex54]

edit: think I figured it out , the gate is a constant signal that is switched between steps with each pulse,
so to answer my own question the length of the pulse has no effect.

 

[Merlin3189]

so to answer my own question the length of the pulse has no effect.

But you have the wrong answer!
If you look at the data sheet page 5 you will see the minimum clock pulse is between 30ns and 200ns.

If you break these limits, there is no guarantee that the circuit will operate correctly (may give false counts) or at all.

The cause may be that bistables need finite time to change state - capacitances have to be charged before voltages reach their significant level, semiconductors need to have charge carriers removed before they become non-conducting for eg.

In other circuits the propagation delays through the circuit may matter, because false logic states may be latched on a falling edge of the clock if insufficient time has been allowed for the logic to reach its correct state. (I think this does not affect the 4017: for this the clock spacing seems to be the critical factor for this latter effect.)

These things don't bother you unless you are operating at MHz speeds (which speeds depend on the technology and the operating voltage.) But if you are, then you need to study the data sheet carefully to ensure it will perform as expected. They do provide a lot of detail.

Edit: removed reference to rise and fall times, which do not apply to 4017, as clock is Schmidt triggered.

 

[AFex54]

But you have the wrong answer!
If you look at the data sheet page 5 you will see the minimum clock pulse is between 30ns and 200ns.

If you break these limits, there is no guarantee that the circuit will operate correctly (may give false counts) or at all.

The cause may be that bistables need finite time to change state - capacitances have to be charged before voltages reach their significant level, semiconductors need to have charge carriers removed before they become non-conducting for eg.

In other circuits the propagation delays through the circuit may matter, because false logic states may be latched on a falling edge of the clock if insufficient time has been allowed for the logic to reach its correct state. (I think this does not affect the 4017: for this the clock spacing seems to be the critical factor for this latter effect.)

These things don't bother you unless you are operating at MHz speeds (which speeds depend on the technology and the operating voltage.) But if you are, then you need to study the data sheet carefully to ensure it will perform as expected. They do provide a lot of detail.

Edit: removed reference to rise and fall times, which do not apply to 4017, as clock is Schmidt triggered.

I should have left the original post there when I edited it,
you needed it to understand what I was asking. the word 'affect' is very misleading without the OP
I was wondering if I could adjust the length of each steps 'gate' to be lower than 100% of the step with a narrower pulse,
sorry for the trouble.

 

[Merlin3189]

No trouble. Sorry I didn't understand what you were asking.