Ok, I see. I overlooked your intended meaning for the phrase "charging
current". You meant specifically current into the capacitor and not total
diode current. That was unclear to me.
However, the correct multiplier is 1.73
Yes, this is what my first graph would show if I extended the vertical
scale a little.
, not 1.5, and for the
[OOPS - off it went before I was finished!]
I take back my casual dismissal of the higher capacitor
dissipation for the actual case of discontinuous current.
The multiplier for 50% rises from 1 to about 1.25, and
for 25% to over 2x, which is certainly very significant.
It's too bad we don't know more about Simon's transformer
turns ratio, etc. One certainly doesn't want to fall
below 50% at full output, if it can be avoided.
Yes, of course, that's right. I stand corrected.
BTW, D is usually defined as the PWM switch-on time,
rather than the PWM power-delivery fraction as I've
used it here, so readers should reverse the D values.
I agree that's what is usually meant by D, but in this discussion we've
been concentrating on the output part of the supply, and I think it's
reasonable to use D for the on time of the diode as long as everybody
understands that's what we mean. I used it that way in my plots on ABSE,
and I understood that's what you meant in your posts here. Until now,
anyway. I'm going to stick with that meaning, because I think it will just
add confusion to change it now.
I explained what I was calculating in words. I used the usual
calculations. For example, the RMS current in the capacitor is the square
root of the integral (over 1 period) of the capacitor current of 1 amp for
D % of the period, squared, and so forth for the other calculations. I
have made mistakes doing this sort of thing in the past, and that's why I
invited others to verify the calculations. I think it would be better if
anybody who did so, came up with their own formulas, the better to provide
The plots vs duty-cycle are
indeed useful, but I do have one comment: showing the
current rising from 0 to full for 0 to 100% duty cycle
is misleading. In reality the power supply might reach
full output at a 50% power-delivery fraction, etc., the
other 50% being used to charge the inductor/transformer.
I should have explained even more precisely, something I'm criticizing
you for. This lack of precision in description is the cause for a lot of
the disagreement in this group! :-(
In the plots, I am considering a supply without feedback, and I made the
peak current into the diode at the beginning of a pulse always 1 amp. In
other words, during the on time of the primary side switch, the inductance
is always charged up to the same current, regardless of duty cycle. I
wanted to normalize things. The main purpose of the plots is to show that
the ripple current in the cap is not always greater or always less than the
output current, a point you were making and others were disputing.
Moreover, as we've used it here, not knowing the supply
design details, a more serious case occurs if we assume
that full power is reached for a lesser fraction than 50%,
such as 25%. That's when things get tough for the poor
capacitor, and surely would represent poor power-supply
design in this case. But that's exactly what happens
for a simple inductor boost regulator, e.g., 25% duty
for a 1:3 step-up ratio at maximum power.
I'll do some more plots, normalized to constant power delivered to the