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filtering decimation of a signal

M

MooseFET

Jan 1, 1970
0
I disagree.  The essence of a limit cycle is a persistent nonzero output
with a zero input.  Its time variation or lack of same is a detail.

In order for something to be a "red apple" it must first be an
"apple". In order for something to be a "limit cycle" it must first
be a "cycle". Since the single pole case doesn't cycle, I don't agree
with calling it some special type of "cycle".
You can if you want, but it doesn't lead to any useful predictions that
I know of.

Well notice the useful prediction that I said it shows about the
single pole IIR and then you will know of a useful prediction that it
leads to.
 What does it mean to say that something has infinite gain
over zero range?

We do that sort of thing all the time. Any time you talk about a step
function you say that it steps from one value to the other over a zero
length time.
 
M

MooseFET

Jan 1, 1970
0
It oscillates because of the quantization error. If the word width was
infinite, it would settle towards it's final value, though you never
reach it.

I agree that there is a quantization error but this does not explain
why there is an oscillation. The system could just stop at a final
value and stay there. It doesn't need to oscillate. Elsewhere in
this thread I showed step by step an example that stopped at an offset
of 4.
 
I have a 100kHz sampling frequency ADC hooked up to an FPGA (CycloneII)
and would like to use a FIR filter to lowpass this signal down to about
50Hz -3dB cutoff frequency. The Quartus FIR builder attenuates DC when
I put 100kHz input and 50Hz output in it, is there a better way to do
this perhaps decimate the input signal or use nested FIR filters? I
would like to get an average of this 100kHz sampled data basically with
about a 5Hz to 50Hz update rate.

A common technique when you have large decimation ratios is to use a
CIC or cascaded integrator comb filter. This is a computationally
efficient way to implement a moving average, and it's usual to apply
it several times (condensed on itself) for a sharper higher-order
response. The response is ultimately a sync function raised to the
power of the order, so it's not quite flat. The fancy way of dealing
with that is to follow up with an FIR filter (at the low decimated
sample rate) having an inverse sync response. The cheater way of
dealing with it is to have the CIC decimate to 4 or 8 times your
desired sample rate, then use FIR's to do the final decimation while
selecting out the relatively flat part in the middle . For most
purposes, the CIC response is "flat enough" in the central 1/8 to 1/4
of its output bandwidth around zero, which is the part you keep.
 
M

MooseFET

Jan 1, 1970
0
You can redefine pre-existing terms if you like, but it doesn't help
communication much.

Your use of the term for an offset is one that I have never seen
before.
  The nonzero output of a first-order IIR filter
with zero input is usually called a 'DC limit cycle',

I have never seen it called that before now. The phrase only gets 96
hits on google so it can't be all that common.

e.g.http://books.google.com/books?
id=aQvLUNWlen0C&pg=PA213&lpg=PA213&dq=%...
(http://tinyurl.com/9c8vgk)

This permits a unified treatment of limit cycles, rather than having to
treat the dc case specially for no reason other than terminology.

In the cases I have dealt with, the DC component is a different
question from the AC one. The AC case can be removed by later
filtering whereas the DC one can't.
I'm using "Useful prediction" in the sense of "engineering result that
helps you understand and fix the problem".

Since the prediction of what I stated has proved very useful to me and
others, I think you are ignoring the usefulness. It answers the
question of whether the system will have an (AC if you insist) limit
cycle. A fairly simple argument based on there being no gain at which
it oscillates settles it for all numerical values.
 
I agree that there is a quantization error but this does not explain
why there is an oscillation.  The system could just stop at a final
value and stay there.  It doesn't need to oscillate.  Elsewhere in
this thread I showed step by step an example that stopped at an offset
of 4.

I reviewed your posts and didn't find the explanation. In any event,
quantization error CAN inject energy back into the system, hence limit
cycles.
 
M

MooseFET

Jan 1, 1970
0
I reviewed your posts and didn't find the explanation. In any event,
quantization error CAN inject energy back into the system, hence limit
cycles.

No, we are talking about the simple case of a single pole IIR filter
working on data that never goes anywhere but being recorded. There is
no route back to the "system".
 
No, we are talking about the simple case of a single pole IIR filter
working on data that never goes anywhere but being recorded.  There is
no route back to the "system".

I view the filter as the system, hence by definition, there is
feedback.

This whole "argument" shouldn't be rocket science. If it is a well
known as you say that a single pole IIR filter doesn't have limit
cycles, it should be some well known theorem. For example, a FIR
filter with symmetric coefficients is linear phase. Your hypothesis
should be a one liner in textbooks.
 
M

MooseFET

Jan 1, 1970
0
I view the filter as the system, hence by definition, there is
feedback.

Do you mean looking at the IIR in complete isolation? If so then we
agree on what we are talking about.
This whole "argument" shouldn't be rocket science. If it is a well
known as you say that a single pole IIR filter doesn't have limit
cycles, it should be some well known theorem. For example, a FIR
filter with symmetric coefficients is linear phase. Your hypothesis
should be a one liner in textbooks.

Since it is obvious that there can't be an oscillation, they may have
left it out of the text books or just stated without proof. Pick the
programming language that you like and construct an IIR filter with
byte variables and try it. Since there is only one constant to set,
you can try a goodly number of cases without working at it too hard.


X[n] = X[n-1] - A * X[N-1]

Where A < 1, can never change the sign of X[]
 
I view the filter as the system, hence by definition, there is
feedback.

Do you mean looking at the IIR in complete isolation?  If so then we
agree on what we are talking about.


This whole "argument" shouldn't be rocket science. If it is a well
known as you say that a single pole IIR filter doesn't have limit
cycles, it should be some well known theorem. For example, a FIR
filter with symmetric coefficients is linear phase. Your hypothesis
should be a one liner in textbooks.

Since it is obvious that there can't be an oscillation, they may have
left it out of the text books or just stated without proof.  Pick the
programming language that you like and construct an IIR filter with
byte variables and try it.  Since there is only one constant to set,
you can try a goodly number of cases without working at it too hard.

  X[n] = X[n-1] - A * X[N-1]

Where A < 1, can never change the sign of X[]

Bingo. Now that makes sense. It was worth the thread.

I recall in Openheim&Shafer, they have a homework exercise where you
allow the accumulator in the FIR to overflow. If the result should
have fit in the word width, then the overflow doesn't matter. It
always seemed to me that they should have offered a proof.
 
M

MooseFET

Jan 1, 1970
0
[....]
Now for the really important question: Is the OP still here or did
they leave long ago?

I don't think an IIR is what he was after.
 
[....]
Now for the really important question:  Is the OP still here or did
they leave long ago?

I don't think an IIR is what he was after.

Oh, who cares. ;-) The thread added to my general knowledge of DSP.
I've only programmed it, i.e. never built any DSP hardware. I had an
interesting project using a coordic which we were going to do in
hardware, but the project got canceled.
 
M

MooseFET

Jan 1, 1970
0
On Dec 27, 8:07 pm, "[email protected]" <[email protected]> wrote:> Bingo.
[....]
Now for the really important question:  Is the OP still here or did
they leave long ago?
I don't think an IIR is what he was after.

Oh, who cares. ;-) The thread added to my general knowledge of DSP.
I've only programmed it, i.e. never built any DSP hardware. I had an
interesting project using a coordic which we were going to do in
hardware, but the project got canceled.

Another little trick that I should throw out here is:

Remainder = 0

Loop:
Error = New - Current + Remainder
Remainder = Error MOD A
Current = Current + Error DIV A
goto loop

By bringing the remainder into the next loop, the offset of an IIR can
be made to go away. It has the advantage over the "always round away
from zero" trick that it is more linear.
 
J

Jamie Morken

Jan 1, 1970
0
MooseFET said:
[....]
Now for the really important question: Is the OP still here or did
they leave long ago?

I don't think an IIR is what he was after.

Still here, just catching up on all the messages. Happy New Year!

cheers,
Jamie
 
J

Jamie Morken

Jan 1, 1970
0
MooseFET said:
MooseFET said:
Bingo.
[....]
Now for the really important question: Is the OP still here or did
they leave long ago?
I don't think an IIR is what he was after.
Still here, just catching up on all the messages. Happy New Year!

... and the best to you and yours.

Did we answer your question?

Yes and lots of good general information too! I think I will try a CIC
filter later but right now am using a 128 sample adder then a 7bit right
shift (to average 128 samples) and then feeding this into a FIR filter.

cheers,
Jamie
 
M

MooseFET

Jan 1, 1970
0
MooseFET said:
MooseFET wrote:
Bingo.
[....]
Now for the really important question:  Is the OP still here or did
they leave long ago?
I don't think an IIR is what he was after.
Still here, just catching up on all the messages.  Happy New Year!
... and the best to you and yours.
Did we answer your question?

Yes and lots of good general information too!  I think I will try a CIC
filter later but right now am using a 128 sample adder then a 7bit right
shift (to average 128 samples) and then feeding this into a FIR filter.

If I was doing it, I'd take at least a few extra bits into the FIR
filter if I could afford the extra hardware.

Or:

Have an extra input to your adder where you bring in the remainder
part from the last divide by 128. The rounding is biased based on the
remainder so that the errors cancel.
 
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