You have a conflict with your definition of behaviour. That's why you can't find a way to implement it!
Look at your first two diagrams. Diagram 1 says that when both inputs are low, the output must be low. But diagram 2 shows a pulse on input 1, with input 2 low, and the output latching into a high state.
Once the pulse on input 1 has gone away, input 1 will return low. Input 2 will be low. And you want the output to stay high. That directly conflicts with diagram 1.
The truth table you've drawn up does not properly define the behaviour you want. That truth table defines the output state for every combination of input states; it is like a truth table for a two-input logic gate. There is no latching or memory involved. Each output is defined simply by a combination of input values.
Going by the truth table, you want the output to be high only when IN1 is high and IN2 is low. You can do this with a two-input AND gate. Feed the first input from IN1, and the second input from IN2 via an inverter. The two inputs to the AND gate will only be high simultaneously when IN1 is high, and IN2 is low.
But you seem to want some latching behaviour. You need to resolve the conflict between diagrams 1 and 2 so you can define a behaviour that is self-consistent.
The behaviour you show in diagrams 2 and 3 is consistent with a set-reset latch, which can be implemented using a 4013. You can also use a 74x74 but the set and reset inputs are active low and both need inverters to get the logic you want. It's only the requirement in diagram 1, that the output is forced low when both inputs are low, that conflicts with that definition.