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FPGA/DSP system design problem

Dear All:

I am thinking about my system, the picture is here:

http://www.flickr.com/photos/26914086@N05/3528643109/sizes/l/

I want to transfer the raw/processed image sensor data to USB 2.0 or
dpram.

Two choices:

1. ADC -> DSP, this means parallel ADC, then DSP processed data ->
USB, FPGA works as a coprocessor, use FPGA's DSP (difficult), FPGA-

2. ADC -> FPGA, this means serial ADC or whatever, then FPGA<----
EMIF---->DSP processed data, data feedbacked from DSP to FPGA -> USB,
DSP works as a coprocessor.
In choice 2, the USB could also connect from DSP but this will
accelerate processed data transfer, decelerate the raw data transfer.

Other questions:

I also need to store raw data, thus the data saving path will be
different:
Choice 1: the raw data will be from ADC -> DSP -> FLASH
Choice 2: the raw data will be from ADC -> FPGA -> FLASH (Is Flash
good for fast data saving, or use EEPROM instead?)

It will meet the same question when I save processed data on board.

The last question is FIFO vs. DPRAM, FIFO could be implemented in
FPGA, could DPRAM be implemented in FPGA? the DPRAM has more
flexibility for sure.

Thanks!
 
If the image data is going on a PC anyway why not just use a USB camera and
and do it in software on the PC.

Bob

Bob

Seriously. You can't get even get close to what a commodity PC offers
you in computing power in an FPGA, for the money.
 
Seriously. You can't get even get close to what a commodity PC offers
you in computing power in an FPGA, for the money.

this is a CCD linear array detector with very fine resolution. This
system will do in real time very fast (sub milisecond).
 
If the image data is going on a PC anyway why not just use a USB camera and
and do it in software on the PC.

Bob

Bob

because I want to run in standalone in the future. I also need to
process real time data on board like deconvolution, dft.
 
J

Jan Panteltje

Jan 1, 1970
0
because I want to run in standalone in the future. I also need to
process real time data on board like deconvolution, dft.

comp.arch.fpga
There are people there that have done things like that.
 
A

Anssi Saari

Jan 1, 1970
0
this is a CCD linear array detector with very fine resolution. This
system will do in real time very fast (sub milisecond).

Is your data rate extremely low then? Just wondering since you
consider EEPROM for storage of raw data and those go to maybe a few
megabits per device?

Just curious since I was involved in a CCD video camera design last
year and one of the major parts of the design was a flash storage
device that could store raw video fast enough. As in, 1920x1080, 12
bpp, 60 fps. Somewhat faster than an SSD drive, for example. Let alone
USB...
 
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