Given a truth table, is there a procedure to follow
in order to draw the logic circuit? For two inputs,
it is easy to guess but it gets difficult when at least three
inputs are involved.
The textbook way for small numbers of inputs (3 or 4 certainly, 5 or 6
with some sweat) is
Karnaugh maps. Looking back I'm not really sure
what they teach or if they really help you any in getting a good
implementation.
Even in the 70's the time-efficient way to do this for more than a few
inputs was with data selectors, see Lancaster's _TTL Cookbook_.
If you're working in FPGA's/GAL's/etc. there are very good computer
tools that essentially just let you put in the truth table and it
implements it in an appropriate way for the technology.
If there are race conditions in decoding (glitches not allowed) things
get more complicated (but many of the automatic tools will handle this
for you too.)
Tim.