global clock (gclk) input at xilinx virtex4 fpga

[Denkedran Joe]

Hi there,

I'm using a Virtex4 FX100 FPGA (package FF1517) in a board design and I
wonder if it is enough to use just one gclk input on the device or if it's
advisable to use more than one due to the large package size...? Does it
make any difference where I put the gclk input(s)? Thank you for your
support...

Regards Joe

 

[Marc Randolph]

Hi there,

I'm using a Virtex4 FX100 FPGA (package FF1517) in a board design and I
wonder if it is enough to use just one gclk input on the device or if it's
advisable to use more than one due to the large package size...? Does it
make any difference where I put the gclk input(s)? Thank you for your
support...

Regards Joe

Howdy Joe,

If the clock tree's within a device is designed correctly (most all of
them are - haven't heard of any problems with V4), then one clock
should work just fine on a device of any size - and is actually
preferable since you only have one clock domain to deal with.

Have fun,

Marc

 

[Tim Wescott]

Hi there,

I'm using a Virtex4 FX100 FPGA (package FF1517) in a board design and I
wonder if it is enough to use just one gclk input on the device or if
it's advisable to use more than one due to the large package size...?
Does it make any difference where I put the gclk input(s)? Thank you for
your support...

Regards Joe

The multiple clock inputs are for when you need to support a board design
that has multiple clock domains, not for driving the same clock to the
whole FPGA.

I would expect that using multiple clock inputs for the "same" clock
would just give you multiple clock domains within the device, with all
the attendant trials and tribulations of synchronizing between them, only
for no reason.

--
Tim Wescott
Control systems and communications consulting
http://www.wescottdesign.com

Need to learn how to apply control theory in your embedded system?
"Applied Control Theory for Embedded Systems" by Tim Wescott
Elsevier/Newnes, http://www.wescottdesign.com/actfes/actfes.html