Wouldn't it be nice to write code in Verilog then _convert_ to an
electronic schematic diagram for analysis, or even _produce_ a PCB from
it and have a working circuit ... by using the same software tool!
Not really. Unless you're doing a really large Verilog design, it'll most
likely fit into a single part (e.g., FPGA or CPLD), so there's little point in
the guys who write Verilog synthesis & place/route tools to try to do PCB
design as well.
The big-guns of HDL simulation -- ModelTech and Aldec -- do have integrated
design entry & simulation, and you can probe around during a simulation on a
"schematic" that contains, e.g., block diagrams of your Verilog modules.
Although they're calling external programs to do it, they also provide
seamless synthesis & place/route from within their IDEs. In general the best
EDA solutions end up using different vendors tools for solving different
problems, but try to tie them all together in a nice "flow."
And I'll look at them later.
