Graph the output waveform of a MOSFET circuit

[akkex]

Hello, I am new in this...

Here I have to graph the output waveform of the circuit for a square input wave, whose peak-to-peak voltage ensures Q2 is polarized in the ohmic region.
Suppose Q2 has RDS (on) = 9Ω and Q1 RD = 8kΩ

please I just need the graph, if someone can simulate in proteus or another simulator and take a photo
i will apreciate to lot it

 

[duke37]

What is the circuit intended to do?
What voltage is needed to turn Q1 and Q2 on.

A normal fet will turn on with 12V or so on the gate. Assuming Q1 is on, this puts 12V on the gate of Q2, turning that on also. The voltage supply is shorted.

Turning off Q1 will allow Q2 to turn off giving an unknown voltage output.

There is little need for a simulation until the circuit does what is intended.

 

[akkex]

What is the circuit intended to do?
What voltage is needed to turn Q1 and Q2 on.

A normal fet will turn on with 12V or so on the gate. Assuming Q1 is on, this puts 12V on the gate of Q2, turning that on also. The voltage supply is shorted.

Turning off Q1 will allow Q2 to turn off giving an unknown voltage output.

There is little need for a simulation until the circuit does what is intended.

The output is a square wave of the same frequency as the input signal but out of phase180º with respect to it, with a maximum voltage of 12 volts and a minimum of 13.5 mV to get the ON

The purpose of the circuit is to observe how the output is a square wave is offset 180º

Can you simulate it? I am bad with that

 

[duke37]

Can you simulate it? I am bad with that

So am I
But I am too old to learn now.

To get the output you want, Q1 should be changed to a resistor or constant current source.

In any case to simulate the circuit you will need voltage input and fet characteristics, neither of which are specified.

 

[hevans1944]

This is a really dumb circuit for "explaining" how MOSFETs work.

With Q2 turned off (gate input voltage is low) there is no conduction path for Q1 source because a load is not specified between Q1 source and ground. Although the gate of Q1 is connected to the drain and to +12 V, this does not in any way specify what the source voltage will be without a conduction path for the source current. With Q2 biased off, there is no conduction path for Q1 source current.

Rather than trying to "model" this circuit, why don't you grab a pair of FETs, wire them up according to the schematic you posted, attach a dual-channel oscilloscope probe to Q1 source/Q2 drain, attach the other oscilloscope channel to a square-wave generator output applied between Q2 gate and ground, and apply +12 V DC between Q1 drain and common. Then you take a photograph of the oscilloscope screen, after properly adjusting the time base and trigger controls, and post it for all of us to see. Maybe the input impedance of the oscilloscope channels will provide sufficient load to make the circuit actually work as you expect.