P
[email protected]
- Jan 1, 1970
- 0
Hi
I am going to use AD9830 DDS IC , in a project but I have some
questions:
1. what is advantages of having 4 phase reg & 2 freq reg ? at worst
case suppose we want to have FSK modulation so we can change
frequency word by interface according to data , without using shifting
between frequency registers or so?
2. how can I use it in digital demodulation ( because we have digital
“demodulation” application in first page of datasheet)?
Why the max frequency is half the master clock?
*******But my main problems:
3. I am going to use 89c51 micro controller for interfacing whit
AD9830 instead of printer port of pc
, according to page 6 of application note for evaluation board for
the AD9830 , it has connected pin 32, 33, 34 ( A0, A1,A2): address
digital input , to D0,D1,D2 ( !!) , as you know when we the input
data changes so the addressing changes & it makes problem ,
shouldn’t we use other different pins in interfacing for
addressing ? can you explain it?
According to application note (page 6) For inputting data we
should use 2 latches ( 74HC574), and in that schematic it uses 2
pulses : LATCHE & LOAD , we know that data enter ( written) to
AD9830 by wr ( active low pulse) ( pin 8 on AD9830) so if we use
only one pin for clocking to 74HC574 instead of j-1 ( latch) & j-31 (
load) ( notice that we use a 8 bit for entering data so we can’t
enter more than a 8 bite each period ) so I think we can enter 8 by 8
bit data and after each 8 bit we send a pulse for a latch to enter
data on inputting buffer of AD9830 , instead of entering 16 bit and
give two pulses LATCH & LOAD , am I right ?
4. according to page 5 of datasheet :
The WR pin is used when writing data to the AD9830. The data is loaded
into the AD9830 on the rising edge of the WR pulse. This data is then
loaded into the destination register on the MCLK rising edge. The WR
pulse rising edge should not coincide with the MCLK rising edge as
there will be an uncertainty of one MCLK cycle regarding the loading
of the destination register with the new data.
If WR pulse rising edge coincide with the MCLK rising edge , the new
data will be loading on the next MCLK rising edge ( in this time the
probability of coinciding will be low) ?or we should active WR pulse
again?
At the end where can I find a “ clear “ photo ( not
schematic ) of AD9830 ‘s evaluation board that elements be
obvious on the photo?!
Any help would be most appreciated .
Payam
I am going to use AD9830 DDS IC , in a project but I have some
questions:
1. what is advantages of having 4 phase reg & 2 freq reg ? at worst
case suppose we want to have FSK modulation so we can change
frequency word by interface according to data , without using shifting
between frequency registers or so?
2. how can I use it in digital demodulation ( because we have digital
“demodulation” application in first page of datasheet)?
Why the max frequency is half the master clock?
*******But my main problems:
3. I am going to use 89c51 micro controller for interfacing whit
AD9830 instead of printer port of pc
, according to page 6 of application note for evaluation board for
the AD9830 , it has connected pin 32, 33, 34 ( A0, A1,A2): address
digital input , to D0,D1,D2 ( !!) , as you know when we the input
data changes so the addressing changes & it makes problem ,
shouldn’t we use other different pins in interfacing for
addressing ? can you explain it?
According to application note (page 6) For inputting data we
should use 2 latches ( 74HC574), and in that schematic it uses 2
pulses : LATCHE & LOAD , we know that data enter ( written) to
AD9830 by wr ( active low pulse) ( pin 8 on AD9830) so if we use
only one pin for clocking to 74HC574 instead of j-1 ( latch) & j-31 (
load) ( notice that we use a 8 bit for entering data so we can’t
enter more than a 8 bite each period ) so I think we can enter 8 by 8
bit data and after each 8 bit we send a pulse for a latch to enter
data on inputting buffer of AD9830 , instead of entering 16 bit and
give two pulses LATCH & LOAD , am I right ?
4. according to page 5 of datasheet :
The WR pin is used when writing data to the AD9830. The data is loaded
into the AD9830 on the rising edge of the WR pulse. This data is then
loaded into the destination register on the MCLK rising edge. The WR
pulse rising edge should not coincide with the MCLK rising edge as
there will be an uncertainty of one MCLK cycle regarding the loading
of the destination register with the new data.
If WR pulse rising edge coincide with the MCLK rising edge , the new
data will be loading on the next MCLK rising edge ( in this time the
probability of coinciding will be low) ?or we should active WR pulse
again?
At the end where can I find a “ clear “ photo ( not
schematic ) of AD9830 ‘s evaluation board that elements be
obvious on the photo?!
Any help would be most appreciated .
Payam