# High Speed Counting Circuit ECL Logic

#### jamie1989

Apr 5, 2017
7
Hi, I need to make a high speed counting circuit for part of a project, Im going to be using ECL logic and the
MC10EP016 ON Semiconductor 1GHz counter, i'm a bit fuzzy on ECL logic though. They have a simple schematic of a cascaded counter here on page 10,
https://www.onsemi.com/pub/Collateral/MC10EP016-D.PDF
I know there's some odd things with ECL regarding the Vbb output, I'm unsure whether it should be grounded or connected to the differential clock input? I'm also unsure what the PE output is used for in the counter circuit, is it just constantly pulled high?

I plan on cascading three counters together, so any tips on implementing this efficiently will be great.

Thanks

#### Harald Kapp

##### Moderator
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Nov 17, 2011
13,716
I admit being quite fuzzy on ECL logic.
regarding the Vbb output, I'm unsure whether it should be grounded or connected to the differential clock input?
In no case connect it to ground.It is a reference voltage used to connect single ended outputs to differential inputs (see here, page 6). In that case conenct Vbb to the inverted differential input. If you already use differental input signals, leave Vbb unconnectd.

I'm also unsure what the PE output is used for in the counter circuit, is it just constantly pulled high?
I'm very unsure, too, especially as there is no PE output on this chip. You surely mean the \PE input?
The function of \PE is explained in tables 2 and 3 of the datasheet: \PE=L -> load parallel data, \PE=H -> count.
Therefore if you do not intend to load parallel data, set \PE=H.

#### jamie1989

Apr 5, 2017
7
Thanks for help, apologies on the late reply. Yes PE input not output! I have made a quick circuit of what I think the circuit should be, I want to get one working before I cascade them. I'm unsure whether I've done the Vtt output voltage correctly, could you possibly confirm? Schematic is attached. Thanks.

#### Attachments

• Schematic Prints.pdf
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#### Harald Kapp

##### Moderator
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Nov 17, 2011
13,716
A few remarks:
1. Ideally you put one 100pF decoupling capacitor right netx to each Vcc pin (C2 is good for one IC). Make sure the connections of the 100pF capacitors to the pins and to ground are as short as possible to minimize the indcutance.
2. When you look at the datasheet page 12 it shows the termination of the output signals with 50 Ω to Vtt. I see 2 issues here
a) The termination should be at the receiver input. In your circuit it is at the driver output. This wil not be as effective as expected in suppressing reflections. Plus note that you'll have to design the layout of th ePCB such that the impedance of the traces is 50 Ω and you'll have to use suitable high speed connectors with matching impedance.
b) The termination voltage Vtt should have a very low source impedance. As shown in your circuit, the impedance of Vtt is ~18 Ω. This will lead to crosstalk between the output signals. You could, for the high frequency components, lower the impedance by a capacitor parallel to R1 and/or R2. Better yet use a voltage regulator set to Vcc-2V. And remember: This circuit should be at the receiving end, notthe driving end.
Additionally I recommend to put pull-up or pull-down resistors to all unused or unconnected inputs to improve stability. Use a comparatively high impedance (e.g. 1 kΩ or more) so a suitable driver can override the static signal when required.

#### jamie1989

Apr 5, 2017
7
A few remarks:
1. Ideally you put one 100pF decoupling capacitor right netx to each Vcc pin (C2 is good for one IC). Make sure the connections of the 100pF capacitors to the pins and to ground are as short as possible to minimize the indcutance.
Great will do!

When you look at the datasheet page 12 it shows the termination of the output signals with 50 Ω to Vtt. I see 2 issues here
a) The termination should be at the receiver input. In your circuit it is at the driver output. This wil not be as effective as expected in suppressing reflections. Plus note that you'll have to design the layout of th ePCB such that the impedance of the traces is 50 Ω and you'll have to use suitable high speed connectors with matching impedance.

Are you saying you have an issue with the schematic on page 12 or how I've implemented the termination? I assume it's mine but I can't see the difference, if so I'm unsure how to terminate at the receiver end, if my receiver ends up being where I have placed the terminal block in the attached schematic above? Also if the traces to the receiver are going to be short can I just use a 50Ω resister to create the 50Ω Impedance of the traces?

b) The termination voltage Vtt should have a very low source impedance. As shown in your circuit, the impedance of Vtt is ~18 Ω. This will lead to crosstalk between the output signals. You could, for the high frequency components, lower the impedance by a capacitor parallel to R1 and/or R2. Better yet use a voltage regulator set to Vcc-2V. And remember: This circuit should be at the receiving end, notthe driving end.

I will go with the voltage regulator, I assume I'll have to pick one with a low enough impedance so as to reduce the back chatter?

#### Harald Kapp

##### Moderator
Moderator
Nov 17, 2011
13,716
I assume it's mine but I can't see the difference
Sorry, yours.
The difference is that the termination should be at the receiver input (a).
You put it at the driver output (b).

As a rule of thumb for 'short' traces termination can be neglected if the rise time of the signal is greater 10 times the delay time of the line (tr > 10*td). Or (by changing the condition to tdr > 7*td)
-> tr (ns) > length (in.) for a typical PCB.
A 50 Ω series resistor is not the same as a stripline with 50 Ω impedance. At the connection between simple trace and resistor there is an abrupt change in impedance which will lead to reflections and consequently to signal distortion.

I assume I'll have to pick one with a low enough impedance so as to reduce the back chatter?
Any off-the shelf voltage regulator will do that for you. For good high frequency response add some capacitors (100pF...1nF) next to the termination resistors connected with as short a trace as possible to ground.

For any high speed design as this I highly recommend using a ground plane in the layout of the PCB.

#### jamie1989

Apr 5, 2017
7
Ok great, I'll redesign the circuit with the recommended. The receiver of this circuit will be a pic microcontroller, the counter will be disabled at some sampling time and the count read from the cascaded counters, is anything else recommended on the receiver side of the circuit in this case, as its ECL to TTL?

#### Harald Kapp

##### Moderator
Moderator
Nov 17, 2011
13,716
is anything else recommended on the receiver side of the circuit in this case, as its ECL to TTL?
Not if the logic levels match.

#### jamie1989

Apr 5, 2017
7
Here is the redrawn circuit attached, I have only included two 100pF capacitors next to the Vcc pins as I would like to reduce the space occupied as much as possible, in the design of the pcb I will make sure that the termination resistors are at the receiver end, C4 is included with the voltage regulator to help suppress noise.

#### Attachments

• Schematic Prints2.pdf
15.6 KB · Views: 51

#### Harald Kapp

##### Moderator
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Nov 17, 2011
13,716
This looks good although I really recommend one capacitor per Vcc pin. A small 0603 size SMD capacitor doesn't take up much PCB real estate.

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