actually its a trainer board expereiment for the BE/BSC students in
lab thats why i want to design it.
For a trainer, it is practical to multiply bytes using an adder and two
shift registers. The algorithm goes something like this:
1. put the multiplicand in a register or have it available on input
switches
2. put the multiplier in a shift register.
2. Inspect the least-significant bit of the multiplier. If it's 1, add
the multiplicand to bits 7..15 of a 16-bit circular shift register, with
the carry going to bit 0.
3. If you haven't looked at the last multiplier bit yet, shift the 16-bit
register 1 bit to the right, shift the multiplier 1 bit to the right
and go to step 2.
After eight shifts, the 16-bit product will be in the circular register.
Instead of using a shift register for the multiplier, you can use a
counter and a multiplexer to point to each multiplier bit.
Four-bit parallel adders and eight-bit shift registers with both serial
and parallel inputs and outputs are available as single chips, so this
isn't hard to breadboard.
It would be instructive to build this, then solve the same problem in
assembly language on a 16-bit microcontroller, then on something like a
BASIC Stamp. I haven't done the cost and timing analyses, but the
microcontroller approach is probably the cheapest. The medium-scale
registers approach could be fastest. Some logic families have
sub-nanosecond gate propagation times, but I doubt that you could make
that work on a breadboard. A BASIC-interpreting microcontroller like the
Stamp would be slower and pricier, but definitely the quickest to
implement.