# How does capacitor C2 discharge ?

#### maker_4rwea2tn_1663572324

Sep 19, 2022
1
I'm new to electronic and I'm learning how transistor tester circuit work :

I understand how C2 charged but I don't how C2 discharge

First it charges on positive side and T1 , T2 off .

When it discharge they flow through R5>>ground>>R3>>R1>> other side of capacitor ?

Second T1, T2 on and It charges on positive side.

When it discharge it will follow this path right?

TOT BE junction>>R2>>ground>>
T1 CE junction>>other side of capacitor.

Thank you.

#### Alec_t

Jul 7, 2015
3,282
TOT BE junction>>R2>>ground>>
T1 CE junction>>other side of capacitor.
No.
The path is R5, C2, TOTbe, R2.

#### Sunnysky

Jul 15, 2016
529
TOT is self-biased with negative DC feedback using R11=100k between C-B and emitter R2 Bypassed for high AC gain. Since T2 has a grounded emitter it also has high gain and inverting thus C2 is "positive AC feedback with gain >>1) which automatically makes it an oscillator. This type of oscillator is called a Relaxation type sawtooth type that uses the positive ramp from T1 cutoff with a negative base-emitter voltage. T1 Vb is [pulled up R1 until Vbe conducts then T2 rapidly saturates with a step that turns off T1 and thus truncates it to a very narrow pulse with a ramp time of R1*C2 = 1 ms approx. or 1 kHz.

The diagram shows the oscillation of one cycle of a sine wave but this is false.

It's just a <1us pulse every 1 ms.

The author just wanted to show (poorly) that there is a signal inversion in the collector output from the base (Common Emitter) somehow with the polarity inversion of a sine wave, even though I know it won't be a sine wave. Just remember that ALL common emitter amplifiers are inverting and two stages in the feedback to base loop make it positive feedback.

So C2 is continually being charged by R1 pullup and pulled down with a step by T2 to discharge the ramp and then cut the pulse short to start another ramp with all the transistors OFF. The speaker is thus OFF, except for narrow 1kHz spikes ( that will sound like a buzz when a transistor is inserted in the socket.

It won't matter if the hFE is 5 to > 100 as the circuit will oscillate by the effects only of R1C2 to the sound of the speaker. But if the NPN C-E is reversed the hFE will be essentially about 1 and will not oscillate as there is sufficient attenuation in R4 to reduce the gain of T2.

The narrow pulse also makes the battery power consumption very small and zero with no transistor in. < 9V/ 100k = 90 uA during the ramp but several watts peak for a < 1us during the pulse.

This is the same circuit simulated in your browser.

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#### Alec_t

Jul 7, 2015
3,282
No.
The path is R5, C2, TOTbe, R2.
Ignore that. I've been corrected.

#### Sunnysky

Jul 15, 2016
529
I will attempt to explain from power-up as follows, but it is almost identical to the basic dual NPN astable vibrator circuit except there is only one flyback cap so there is only one sawtooth polarity.

1. The initial condition for C2 & C1 = 0V thus Vbe=starts near 0 with weak pullup from R1=100k on the left side of C1.
2. The right side is at 0V since T2 is also OFF and 4k7 pulls it down.
3. Within 20 us or so Vbe slowly conducts and charges up T1-e cap by the low current until T1-Vbe exceeds 600 mV which is sufficient to sink 1 mA and turn on T2 very fast

The arrows shows the flow of current that affects the voltage on each part according to it's impedance. Ignore the speaker RLR model for now.

4. T2-c pulls up the right side of C2 to near 9V minus Vce(sat)<=0.1V of PNP while the left C2 or T1-b clamps that Vmax to < 1V thus C2 sees -8V across it for a moment
5. This abruptly causes T1 to conduct and pull down T1-c and T2b but the T1-b only has to decay a xxx mV to turn off T1& T2 so this SCR like LATCH is C2 coupled and thus shuts itself off quickly.

6. When the pulse shuts off T1 & T2 C2 is fully charged but now drop to near 0V on the right side thus the T1-base is now reverse biased excessively > -6V which can stress induce a fault! just like the typical NPN+NPN relaxation oscillator. So a Pro Designer might put a zener or negative diode clamp on T1-eb or reduce the supply voltage to 5V. But this begins the rising sawtooth from -V to Vbe=> 0.5V enough to pull down collector and turn on T2. This then repeats and the C2 capacitor will see up to 2x the supply voltage as this

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