Maker Pro
Maker Pro

Hybrid capacitors

A

acd

Jan 1, 1970
0
In many cases supply voltage is filtered by combinations of small (1n-100n) ceramic and larger (say 100uF) tantalum/electrolyte capacitors.
Since each extra component requires some space around it for manufacturability I was wondering whether there are
hybrid capacitors that combine two types (low ESL, large capacity)
capacitors in one package. Of course, it would need a special landing pattern in order to preserve the low inductivity.
Price would be higher and the question which combinations would
be appropriate, but the space savings could open a marker for mobile devices, medical, etc.
I found this article, but it discusses ceramic-only:
http://www.ceramicindustry.com/articles/91910-pcb-space-improvements

Maybe I missed it, and something like this exists already?

Regards,
Andreas
 
Exactly. Most of those articles have at least one author who works for
a capacitor company.

There are people who seriously recommend using hundreds of bypass caps
per FPGA.

Including 'X' and 'A'.
 
R

rickman

Jan 1, 1970
0
Including 'X' and 'A'.

I've had this conversation with 'X' and they admit that they make their
recommendations based on a lack of knowledge about their customer's
designs because the designs vary across the map. Their recommendations
are based on the worst case ever possible FPGA design with a huge dose
of CYA thrown in.

On the other hand, I have taken a class in high speed digital design
with someone who used theory, then simulation and finally testing on
boards built to test power delivery system designs and came to the
conclusion that mixed capacitor values and a much smaller number of caps
than are typically used are the best approach for digital designs.

Specifically, he used an approach of actually calculating impedance at
various frequencies compared to the required impedance calculated for
the application. No rules of thumb, no guess work.

Rick
 
I've had this conversation with 'X' and they admit that they make their
recommendations based on a lack of knowledge about their customer's
designs because the designs vary across the map. Their recommendations
are based on the worst case ever possible FPGA design with a huge dose
of CYA thrown in.

Sure, they admit that but it really is a huge dose of CYA in even the worst
case. I generally try to add the capacitance recommended then just no-pop a
good share of them. It's a lot easier to add caps if the footprints are
already there. BTW, I've never had to.
On the other hand, I have taken a class in high speed digital design
with someone who used theory, then simulation and finally testing on
boards built to test power delivery system designs and came to the
conclusion that mixed capacitor values and a much smaller number of caps
than are typically used are the best approach for digital designs.

I've seen people simulate just about every fool thing. I stopped blindly
trusting simulations long ago. ...particularly other people's simulations.
Specifically, he used an approach of actually calculating impedance at
various frequencies compared to the required impedance calculated for
the application. No rules of thumb, no guess work.

I've seen that done, too. It works, but so does sprinkling a few caps around.
They're cheap.
 
R

rickman

Jan 1, 1970
0
Sure, they admit that but it really is a huge dose of CYA in even the worst
case. I generally try to add the capacitance recommended then just no-pop a
good share of them. It's a lot easier to add caps if the footprints are
already there. BTW, I've never had to.


I've seen people simulate just about every fool thing. I stopped blindly
trusting simulations long ago. ...particularly other people's simulations.

Did you read the part about building a board to test the issue? He has
verified this every way you might want.

I've seen that done, too. It works, but so does sprinkling a few caps around.
They're cheap.

Depends on how many... 10-20 per board times X can be a lot of dollars.
On the other side, if you use have too few on the board and your
design is actually more sensitive than you expected... well, that's why
engineering isn't just winging it.

Rick
 
T

Tim Williams

Jan 1, 1970
0
rickman said:
I've had this conversation with 'X' and they admit that they make their
recommendations based on a lack of knowledge about their customer's
designs because the designs vary across the map. Their recommendations
are based on the worst case ever possible FPGA design with a huge dose
of CYA thrown in.

On the other hand, I have taken a class in high speed digital design
with someone who used theory, then simulation and finally testing on
boards built to test power delivery system designs and came to the
conclusion that mixed capacitor values and a much smaller number of caps
than are typically used are the best approach for digital designs.

Specifically, he used an approach of actually calculating impedance at
various frequencies compared to the required impedance calculated for
the application. No rules of thumb, no guess work.

I once tried the power supply impedance calculator from Altera, which does
much the same thing. I had reasonable results after a little work.

Input rough dimensions of how much plane you're going to have, physical
dimensions, vias, traces, that sort of thing, and it'll guess how many
bypass caps you need.

Of course, its first guess is something like 4 x 0603s, 9 x 0402s and some
0201s if you can even see them, plus whatever tantalums it can find.

After poking around a bit, I found excellent results with a single, fairly
bulky tantalum, and a small number of 0603 0.1's per I/O bank (this was a
middle size Cyclone).

It's worth noting that results are almost always *WORSE* using a low-ESR
bulk cap, like an aluminum polymer. This is because it short-circuits the
series resonances, making things a lot worse. The ESR of a tantalum (or,
if you can accept the variance in ESR, aluminum electrolytic) dampens it
much better than staggered values or huge arrays of similar values.

Tim
 
Did you read the part about building a board to test the issue? He has
verified this every way you might want.

He verified that it worked. He likely didn't verify that a lesser amount
didn't. Hell, cover the thing with caps and it'll work.
Depends on how many... 10-20 per board times X can be a lot of dollars.
On the other side, if you use have too few on the board and your
design is actually more sensitive than you expected... well, that's why
engineering isn't just winging it.

Not *nearly* as much as too little and finding out about it a year later.
 
A good opportunity for Muntzing, though, if you have the space. Lay out
more decaps than you think you need, and then don't populate all of
them.

That's essentially what I do. On my last board, the board stuffer did it for
me though. ;-( ...still worked fine. I won't take them off this spin,
though.
 
0603's aren't bad. 0402's are nasty little critters. 0805's are
starting to look huge to me, but we use all 0805s on lower density
boards, because production likes them.

Almost everything we do is 0402s, now. In fact, Murata doesn't want us using
0603s for small (<100pF or so) caps. We don't use 0201s for reliability
reasons, though it looks like there won't be much choice soon.
On a multilayer board, 10 caps per power plane is a lot. We use three
or four bypass caps per FPGA per supply voltage, all the same value.
That always works, so is probably too many.

I tend to use .1uF caps with a few at whatever capacitance is needed to have
the SRF at the clock frequency. Of course there are larger bulk caps at the
supplies and at really high current devices.
 
R

rickman

Jan 1, 1970
0
He verified that it worked. He likely didn't verify that a lesser amount
didn't. Hell, cover the thing with caps and it'll work.

You aren't grasping the concept. He didn't build a board for some
application and verify that it worked the way he designed it, he built a
board just to test the functionality of decoupling caps in the analysis
and simulation that he did. He primarily disproved the myth of the
inductive loop of cap and power/ground pins being the determining factor
in a system using adequate power/ground planes. Rather the power/ground
planes couple the cap to the pins as a transmission line providing all
the current the pins need until the wave front reaches the cap and the
cap can supply the current. The size of and therefore the inductance of
the loop is not directly relevant in this case.

That is the basis of the myth of needing a cap for each power pin. Once
you dispel that myth you can then focus on the impedance of the PDS over
frequency and optimize the number of caps for cost and board area vs
impedance.

Not *nearly* as much as too little and finding out about it a year later.

So how do you ever know you have enough if you don't do an engineering
analysis? Do you just keep adding caps until you can't lift the board
anymore?

Rick
 
You aren't grasping the concept.

No, you're not grasping the "existence theorem".
He didn't build a board for some
application and verify that it worked the way he designed it, he built a
board just to test the functionality of decoupling caps in the analysis
and simulation that he did.

And fewer would almost surely have worked, as well.
He primarily disproved the myth of the
inductive loop of cap and power/ground pins being the determining factor
in a system using adequate power/ground planes. Rather the power/ground
planes couple the cap to the pins as a transmission line providing all
the current the pins need until the wave front reaches the cap and the
cap can supply the current. The size of and therefore the inductance of
the loop is not directly relevant in this case.

Only for small values of capacitance and because the ground plane *is* a cap.
That's something that JL has been saying here for some time.
That is the basis of the myth of needing a cap for each power pin. Once
you dispel that myth you can then focus on the impedance of the PDS over
frequency and optimize the number of caps for cost and board area vs
impedance. 1

So how do you ever know you have enough if you don't do an engineering
analysis? Do you just keep adding caps until you can't lift the board
anymore?

Good Lord, you lefties really are stupid.
 
T

Tim Williams

Jan 1, 1970
0
John Larkin said:
There must be, somewhere, an analysis of an infinite-sheet
parallel-plate transmission line, as seen from one point on the plane.

Why not do it yourself? The equations are simple to set up.

I think you'll find it doesn't have a very well defined impedance, though.
The reason is apparent when you run the numbers. Propagation is radial so
the wave front width increases.

More interesting than viewing it as a transmission line (which would be an
axially driven, cylindrical or coaxial resonator structure) is its
inductance, which follows a similar law.

Tim
 
Top