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I need explanation of circuit gains I'm seeing

Trent

Apr 17, 2010
16
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Apr 17, 2010
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I've been designing a simple dual FET Wheatstone bridge using the website "www.falstad.com/" which allows one to draw a circuit very easily and it shows how it runs and does all the calculations. It's very simple to use.

I've attached a pic of a typical circuit.

The transistors used in the simulation are supposed to be MPF102 n-JFETs, with Vp= -8V, and a 20mA limit.

By playing with bias resistor values, I've gotten some unusual results.

The attached graph and table of my data shows a range of values for FET gain, gm, and the signal amplitudes I got for each circuit I tried.

In the very high signal amplitude circuits, the resistor settings are extremely touchy. Small changes can send the amplitude from the mV range down to the uV range.

My questions are:
1. These high signal amplitudes don't seem possible, are they a fluke of the calculations?
2. Why should circuits with low FET gain, gm, have high signal amplitudes and vice-versa?
3. Why don't the circuits with the highest gm have the highest signal amplitudes?
4. Looking at the chart, which values should I strive for? High gm but lower signal amplitude (assuming these amplitudes are actually possible)? Or, low amplitude, with high gm value?
Or, should I look at some combination of the other FET parameters?

Thanks
 

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poor mystic

Apr 8, 2011
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I wonder whether it behaves the same way in the real world? Or you could try it in SPICE.
 

Trent

Apr 17, 2010
16
Joined
Apr 17, 2010
Messages
16
The only spice program I have is "5Spice" and I haven't learned how to use it fully yet. The website mentioned is easier to use.
I haven't tried this particular circuit in real life. I was hoping the simulation would help me tune it, but now I don't know which parameters to tune it to.
I don't have a signal generator so I can't measure my input vs output signals in real life.
 
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