Inverted logic is the one thing that gives people the most trouble.
You are pretty much conditioned to think 0v = low = off and Vcc = high = on.
This works for all the standard gates and logic because they are "positive logic"
However, occasionally (well, more than occasionally) the designer will decide that rather than the signal required to activate something being a high signal, it will be a low signal.
This inverted (or negative) logic kinda means that to turn something on, you have to turn it's input off.
So why would this be done?
Look at the most common use of a 555, as a astable oscillator. Essentially a capacitor is charged until it gets to about 2/3 Vcc at which time the voltage across the capacitor is detected by the 555 as a signal to start discharging.
This is positive logic, active high, and triggers (internally) a bistable to change state. This is pin 6, an input -- threshold. It is related to pin 5 (control), but this later pin is typically left either disconnected or connected to ground by a capacitor. Pin 6 is connected to the timing capacitor.
The capacitor is discharged via the discharge pin (7). This is an output which is effectively switched to ground by the flip flop (that has been triggered by pin 6 going above 2/3 Vcc. Typically this is also connected to the capacitor, but via a resistor to limit the discharge current, but also to provide a known discharge rate. To add a little confusion, this pin is also normally connected to Vcc via a resistor which is the charging route for the timing capacitor. Note that pin 7 (an output) is active low. When it's doing its discharge think it is pulled to ground.
Pin 2 (trigger) is an active low input. A trigger event happens when the voltage on this pin falls below 1/3 Vcc. As far as triggering is concerned, high is off (untriggered) and low is ON (triggered). This matches the discharge pin's inverted logic. It matches it for a very good reason. The discharge pin, when low will be discharging the timing capacitor. Pin 2 is also connected to the capacitor (pins 2 and 6 are typically connected together so that they sample the same voltage). As this drops to below 1/3 Vcc, this is activated, and it changes the state of the internal flip flop. This turns off the discharge pin (7), and the capacitor can start to charge again.
Things happen a little differently when wired as a monostable or bistable, but the same inverted logic exists on some pins because they are designed to detect a voltage falling through a particular level vs the positive logic which is there to detect a voltage rising through a particular level.
In digital circuits (the 555 is a bit of an analog/digital hybrid) inverted vs normal logic can be used to detect falling vs rising edges (we call a transition from low to high a rising edge, and the transition from high to low a falling edge). In digital circuits the rise and fall times can typically be assumed to be near zero, and so we care less about the actual switching level. In the 555 we deliberately slow that transition so we can mark time with it.
edit: so why it's dome in a 555? It's done because you're measuring a falling voltage on a capacitor and it would make little sense to need a signal to go high when the capacitor's charge falls below some point. It would require additional complexity in the circuit that inverted logic neatly gets around.