IC4017 - Construction

[Karthik rajagopal]

Hello all,
While referring the datasheet of IC4017, I came across its internal logic diagram.
It was a ring counter implementation using Johnson counter and some additional gates. While reading through the reasons for such an implementation, I came to know that they have used that approach to reduce the number of flip flops.
Since, flip flops are anyway constructed with basic gates and can reduce the need for additional combinational circuit, why do we go with the first approach (as in datasheet)?
Link
Thanks in advance

 

[Harald Kapp]

I came to know that they have used that approach to reduce the number of flip flops.

I can't find that info in the datasheet.

Since, flip flops are anyway constructed with basic gates and can reduce the need for additional combinational circuit, why do we go with the first approach

One master-slave Flip-Flop is equivalent to 8 NAND gates. Is that reason good enough?

 

[Karthik rajagopal]

I can't find that info in the datasheet.

It was not mentioned in the datasheet. I read it from this website - "The counter circuit in the CD4017 however, is not a standard ring counter. Instead, it uses a technique called a Johnson counter that makes it possible to achieve the same with only 5 flip-flops plus some logic gates."

One master-slave Flip-Flop is equivalent to 8 NAND gates. Is that reason good enough?

With D-flip flops (as per the circuit diagram), we are not going to have any race condition.
Please correct me if I am wrong.