I had a look at SimPLL from AnalogDevices. It just supports their

PLLs though. With one of theirs I wasn't able to get better than

-120 dBc/Hz.

On my own, I'd have a tough time in simulating my own PLL.

How does a divider come in ?

I tend to doubt rms jitter numbers of 3ps, they are likely not

able to measure it then.

Rene

Measuring 3ps RMS isn't difficult - the OC-48 parts I've designed (at

2.488GHz) come in at around 1.5ps RMS. We measure them with a Tek

Communications Signal Analyzer. Even so, my noise is over 120dBc/Hz until

around 15MHz (it goes below 110dBc at roughly 10kHz).

The divider introduces a gain factor in the loop, and effectively

multiplies the noise from your reference (imagine that the loop keeps the

noise at the summing node constant - if that's the case, then the noise at

the VCO side of the divider must be scaled by the divider ratio).

To model the divider, consider the effect it has on the noise in the time

domain. Assume the noise is white, and in the time domain it causes t

seconds of jitter (RMS). The equivalent phase jitter is 2*pi*t/T, where T

is the signal period. At the divider output, the time domain jitter is

unchanged - it is still t seconds RMS, assuming the divider doesn't

contribute significant amounts of noise. However, since the period of the

divider output is M*T, where M is the divider ratio, the equivalent phase

noise at the divider output is t/M. In the ideal PLL loop equations, a

divide by M becomes a 1/M scale factor.

-- Mike --