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[Layuot] Why more fingers less parasitic capacitance?

B

boki

Jan 1, 1970
0
Dear All,

In CMOS layout, why more mos fingers we get less parasitic capacitance?

Share dran/source?


Thanks.

Boki.
 
P

Paul Burridge

Jan 1, 1970
0
Dear All,

In CMOS layout, why more mos fingers we get less parasitic capacitance?

Maybe your fingers are in series. Most people have parallel fingers.
 
J

Jim Thompson

Jan 1, 1970
0
Dear All,

In CMOS layout, why more mos fingers we get less parasitic capacitance?

Share dran/source?


Thanks.

Boki.

Draw the layout for both cases and then you will see. You'll need
spacing rules so that you can do the layout properly. I assume you
are in a university where this information should be available.

...Jim Thompson
 
B

Boki

Jan 1, 1970
0
Thank you, of course, we have design rules, I had tape out several times.

I designed several type of 1-V Switched-Capacitor Switched-Opamp
Sigma-Delta Modulator,

I need mos/cmos to be switch, so, the parasitic capacitance is a big problem
to input signal,

My conclusion, if chip area is available, minimum width of mos with maximum
fingers will be the best switch, and the NMOS:pMOS ratio is 1:4

Q: The fingers decrease the parasitic capacitance, becasues shrare source
and drain?


Thanks for every reply.

Best regards,

Boki.
 
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