LDO analysis problem

[jutek]

Hello everyone.

I am new here, welcome everybody.

I have a problem during simulating the LDO.

When i use high load RL=12 Vout=1.2V so Iout=100mA everything is
correct, i can maintain the stability and the transient response is
quite ok.

But when i use low load case, the open loop gain of the whole LDO
decreases very much and has different shape than open loop gain of the
opamp. The pass device is PMOS. Do i do sth wrong during the simulation
or i should math gain, pole/zero position better.

I did the optimalization in the hspice and it didn't find the solution

Any ideas??

regards luke

 

[Pooh Bear]

Hello everyone.

I am new here, welcome everybody.

I have a problem during simulating the LDO.

When i use high load RL=12 Vout=1.2V so Iout=100mA everything is
correct, i can maintain the stability and the transient response is
quite ok.

But when i use low load case, the open loop gain of the whole LDO
decreases very much and has different shape than open loop gain of the
opamp. The pass device is PMOS. Do i do sth wrong during the simulation
or i should math gain, pole/zero position better.

I did the optimalization in the hspice and it didn't find the solution

Any ideas??

What exactly are you simulating ? Are you designing a regulator chip ?

Graham

 

[Jim Thompson]

Hello everyone.

I am new here, welcome everybody.

I have a problem during simulating the LDO.

When i use high load RL=12 Vout=1.2V so Iout=100mA everything is
correct, i can maintain the stability and the transient response is
quite ok.

But when i use low load case, the open loop gain of the whole LDO
decreases very much and has different shape than open loop gain of the
opamp. The pass device is PMOS. Do i do sth wrong during the simulation
or i should math gain, pole/zero position better.

I did the optimalization in the hspice and it didn't find the solution

Any ideas??

regards luke

Take a look at the LoopGain part on my website, adapt it to HSpice,
and watch the _true_ LoopGain and LoopPhase.

The difficulty is probably the change in gm of your pass device with
load.

...Jim Thompson

 

[jutek]

What exactly are you simulating ? Are you designing a regulator chip ?

yes, the ldo will be a part of the system

 

[jutek]

Take a look at the LoopGain part on my website, adapt it to HSpice,
and watch the _true_ LoopGain and LoopPhase.

why can't i simply open the loop and measure gain and phase here?
the results will not be accurate?

 

[Klaus Kragelund]

You can only measure loop gain/phase if the insertion point has low
impedance (for example at the output of a power supply and back to the
error amp)

Regards

Klaus

 

[Jim Thompson]

You can only measure loop gain/phase if the insertion point has low
impedance (for example at the output of a power supply and back to the
error amp)

Regards

Klaus

Neeeerp! Ever hear of Middlebrook's method?

...Jim Thompson

 

[josh lawton]

You can also use return ratio and other methods, but in general for a
regulator using a capcitor and a inductor will not lead to any problems.
I do not think this is the question. It sounds like he sees a loss of
phase margin in the AC responce so I would assume he has no issue with
plotting the gain and phase.

You need to analyize the circuit keeping in mind the loads effect on the
ac responce. You likely need to add a zero in the responce. One other
method to help stabilize a LDO is to add some current draw under low
load conditions.

I am suspisous about the design. With 12V 100mA and 1.2V output you
have ~1.1W. This will really heat up the device a lot unless you can
use some thermally enhanced package.

Josh

 

[jutek]

It sounds like he sees a loss of
phase margin in the AC responce so I would assume he has no issue with
plotting the gain and phase.

so why the transient response seems to be correct more or less?

You likely need to add a zero in the responce.

yes, i added zero, serial resistor and capacity, but when i use .pz it
also adds pole in this freq

method to help stabilize a LDO is to add some current draw under low
load conditions.

i will do it later, first i have to model it and make it working. then
i'll choose topology and will try to meet the spec.

I am suspisous about the design. With 12V 100mA and 1.2V output you
have ~1.1W.

Did I write 12V at the input? i must have been tired. The input is 1.7

regards

luke

 

[Kevin Aylward]

Neeeerp! Ever hear of Middlebrook's method?

I would say for many/most circuits, one doesn't need the full
complication of Middlebrook's method. A voltage source in the feedback
loop, and taking the ratio of each side is usually accurate enough. The
reason is that you only need the full approach (includes current) if the
amp output impedance is high compared to the feedback load. For example,
if the bugger is a regulator with 1uf on the output, the output
impedance at HF is negligible.

And my poetic licence bit..SuperSpice does this all automatically...

Kevin Aylward
[email protected]
http://www.anasoft.co.uk
SuperSpice, a very affordable Mixed-Mode
Windows Simulator with Schematic Capture,
Waveform Display, FFT's and Filter Design.

 

[Robert Baer]

why can't i simply open the loop and measure gain and phase here?
the results will not be accurate?

What you do is put a generator in series with the feedback or
feedforward part of the loop; that keeps the loop closed when that
generator is set to zero.

 

[Fred Bloggs]

Hello everyone.

I am new here, welcome everybody.

I have a problem during simulating the LDO.

When i use high load RL=12 Vout=1.2V so Iout=100mA everything is
correct, i can maintain the stability and the transient response is
quite ok.

But when i use low load case, the open loop gain of the whole LDO
decreases very much and has different shape than open loop gain of the
opamp. The pass device is PMOS. Do i do sth wrong during the simulation
or i should math gain, pole/zero position better.

I did the optimalization in the hspice and it didn't find the solution

Any ideas??

Your problem is inadequate SPICE modeling of the PMOS subthreshold, or
weak inversion, mode of operation. The simulation is not to be trusted
no matter what type of results it produces. A well-known LDO design
engineer was kind enough to publish an article on the types of problems
encountered and ways of modifying the simulation to produce much more
realistic results- but its exact location escapes my damaged brain at
the moment.

 

[Jim Thompson]

Your problem is inadequate SPICE modeling of the PMOS subthreshold, or
weak inversion, mode of operation. The simulation is not to be trusted
no matter what type of results it produces. A well-known LDO design
engineer was kind enough to publish an article on the types of problems
encountered and ways of modifying the simulation to produce much more
realistic results- but its exact location escapes my damaged brain at
the moment.

Somehow the power MOSFET manufacturers will need to be convinced that
Spice modeling at Level=1 or 3 is NOT adequate.

Some time back I did a quicky approximation to some of Win's data to
show that the Level=7 model is necessary to fit subthreshold.

...Jim Thompson

 

[jutek]

Fred Bloggs wrote

Your problem is inadequate SPICE modeling of the PMOS subthreshold, or
weak inversion, mode of operation.

it seems to be, but i use hspice level 49 model so i think that my
macromodel of opamp causes errors. i even found one error.

if you recall the name of this engineer, please write it here. wasn't it
prof. Rincon-Mora?

regards