legg said:
Trouble is with leakage - the importance of sub-microamp drain leakage
in mosfets not being specifiable.
RL
Do you not mean "not in the datasheet"?
The nanoamp region is very achieveable.
Since the OP wanted a low Vf diode, the problem with FETS is that the
gate control is sensitive to temperature, so a fixed bias scheme for
enhancement *or* depletion mode FET is a bit iffy - especially in this
case where the gate control voltage is going to change only a few
hundred millivolts.
Now that temperature sensitivity can be compensated some with a
scheme similar to my first Codatron (TM) design; the patent for that has
been released into the public domain - so feel free to use as you see fit.
Be advised that there can be some mis-matching between FETS, so that
for this "low Vf" application, that can have a large effect on the total
operation if multiple composite devices are needed (read: volume
production greater than 1000 per day).
That can be mitigated to a degree by making it as IC, wafer testing
offset before breakout and use.
Shoot, one could even trim one of the FETs my having graded sizes for
cutting out small areas; and the bias offset can also be trimmed (refer
to the ALD110800 series).