Many ADC sigma delta synchronization

[pardon_232000]

Hello,

i have a question about ADC sigma delta and synchronization. Something
i do not understand.

In a particular design, two ADCs sigma delta (on different board)
using the SAME shared remoted clock (on a third board) must give
synchronized samples.

I thought that if one board reset. The soft has just to maintien the
ADC in the stoped state (after the board is power up again after
reset), waiting a little in order to let the shared remoted clock (or
local CPLD let the clock signal) reach the ADC and then (at ANY time)
let the ADC start acquisiton (leave the low power mode).

As i thought that the S/H operation of the ADC is done on the rising
edge of the clock signal, i thought that sample of the two board will
be exactly synchronize.

But it seams that these action will not ensure that sample of two
board will be synchronize and that the correct way to do that is to
1) Stop the two ADC
2) and restart at the same time the two ADCs in order to ensure sample
synchronization.

Why ?
Thanks for your help...

 

[Bill Sloman]

Hello,

i have a question about ADC sigma delta and synchronization. Something
i do not understand.

In a particular design, two ADCs sigma delta (on different board)
using the SAME shared remoted clock (on a third board) must give
synchronized samples.

I thought that if one board reset. The soft has just to maintien the
ADC in the stoped state (after the board is power up again after
reset), waiting a little in order to let the shared remoted clock (or
local CPLD let the clock signal) reach the ADC and then (at ANY time)
let the ADC start acquisiton (leave the low power mode).

As i thought that the S/H operation of the ADC is done on the rising
edge of the clock signal, i thought that sample of the two board will
be exactly synchronize.

But it seams that these action will not ensure that sample of two
board will be synchronize and that the correct way to do that is to
1) Stop the two ADC
2) and restart at the same time the two ADCs in order to ensure sample
synchronization.

Why ?
Thanks for your help...

The sigma-delta ADC processing and sampling cycle extends over many
cycles of the clock - of the order of thousands, depending on the
resolution of the A/D converter.

This true of most types of A/D converter, with the exception of
single-stage flash converters - for successive approximation A/D
converters the multiplier goes down to something of the order of ten
cycles.

You need to read a decent text-book that explains how A/D converters
work. Horowitz and (Winfield) Hill's "The Art of Electronics" ISBN
0-521-37095-7
isn't too bad, though the 2nd edition waas published in 1989 and
sigma-delta converters have come on a bit since then - Win Hill may
precis the relevant bit of the (as yet unfinished) third edition here
if we are lucky.