Maybe silly question about first-order sigma-delta modulator

K

[email protected]

Jan 1, 1970
0
I'm designing a simple first-order sigma-delta modulator with RC
integrator.

Now I want to define the minimume and maximum sampling frequency of
this modulator. Of course, minimume fs can be found by investigating
the integrator output voltage --- if the fs is too low, the output
voltage will be too high to implement.

However, the maximum fs is hard to achieve. Will the system be
unstable when fs is too high? Is the maximum sampling frequency
related to the bandwidth or gain of the integrator? And How to predict
the frequency?

I'm a rookie in this field and maybe it's a silly question

But still hope to see your opinions. Thanks.

M

MooseFET

Jan 1, 1970
0
I'm designing a simple first-order sigma-delta modulator with RC
integrator.

Now I want to define the minimume and maximum sampling frequency of
this modulator. Of course, minimume fs can be found by investigating
the integrator output voltage --- if the fs is too low, the output
voltage will be too high to implement.

However, the maximum fs is hard to achieve. Will the system be
unstable when fs is too high? Is the maximum sampling frequency
related to the bandwidth or gain of the integrator? And How to predict
the frequency?

I'm a rookie in this field and maybe it's a silly question

But still hope to see your opinions. Thanks.

Walk around the loop and add up the delays. Don't count the
integrator. When the delay is such that the news that the output of
the flip-flop changed doesn't get back around to the input with enough
setup time, the modulator will stop working right.

K

[email protected]

Jan 1, 1970
0
Walk around the loop and add up the delays.  Don't count the
integrator.  When the delay is such that the news that the output of
the flip-flop changed doesn't get back around to the input with enough
setup time, the modulator will stop working right.

I added some delay into my D flip flop and found that SNR started to
decrease when the delay is larger than the sampling period.

I'm not sure what I did is proper for testing the effect of the delay.
And also, I haven't seen any unstable things happen in the modulator,
the only change is that SNR dropped about 10dB.

Does it prove that the maximum sampling frequency is just (1/delay
time)?

M

MooseFET

Jan 1, 1970
0

I added some delay into my D flip flop and found that SNR started to
decrease when the delay is larger than the sampling period.

I'm not sure what I did is proper for testing the effect of the delay.
And also, I haven't seen any unstable things happen in the modulator,
the only change is that SNR dropped about 10dB.

Does it prove that the maximum sampling frequency is just (1/delay
time)?

The real situation is alway more complex than the simple model. The
delay in logic circuits an comparators is not really fixed times.
Comparators have less delay at larger overdrive levels. When the
noise increases, it means that the comparator is getting a bigger
signal so its delay decreases.

Most of the very fast comparators are really just very high gain
amplifiers. They don't contain any positive feedback because adding
it would slow them down. This means that the rise time of the output
depends on the overdrive like the delay time does. The logic that is
connected to this will not really have a simple setup time. A slower
signal will need more setup than a faster one because the input
section also looks like an amplifier.

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