Modelling JFET with unbiased gate

[Robert Strand]

Hi,

I though I'd throw this one up for interest, mainly because this is one
isn't modelled properly by spice. I haven't done any measurements to derive
the answer.

As an example consider a simple common source (for the sake fo the argument
N-channel) JFET amplifier where there are no DC paths to the gate only an
AC coupling of a capacitor to the gate.

Now consider the quiescent point. Take the case where the DS voltage isn't
too low, say above 10V. There will be a potential gradient through the
N-channel and the distributed gate will be distributed through this
gradient - this makes the VGS voltage ill- defined. For the purpose of
modelling I considered the distributed JFET as two JFETs in a kind of
cascode connection, except the gates of the two JFETs are joined. Leakage
in the top JFET's DG junction will forward bias the GS diode of the lower
JFET hence the lower JFET will be fully on. Since the P-gate is of low
resistance it will remain at a constant potential of ~0.3V, this pins the
gate of the upper JFET to 0.3V above the source of the lower JFET.

The tricky question is what is the effective channel lengths of the two
JFETs, and would this be a function of the overall DS voltage.

Rob

 

[Ban]

Hi,

I though I'd throw this one up for interest, mainly because this is
one isn't modelled properly by spice. I haven't done any measurements
to derive the answer.

As an example consider a simple common source (for the sake fo the
argument N-channel) JFET amplifier where there are no DC paths to the
gate only an AC coupling of a capacitor to the gate.

Now consider the quiescent point. Take the case where the DS voltage
isn't too low, say above 10V. There will be a potential gradient
through the N-channel and the distributed gate will be distributed
through this gradient - this makes the VGS voltage ill- defined. For
the purpose of modelling I considered the distributed JFET as two
JFETs in a kind of cascode connection, except the gates of the two
JFETs are joined. Leakage in the top JFET's DG junction will forward
bias the GS diode of the lower JFET hence the lower JFET will be
fully on. Since the P-gate is of low resistance it will remain at a
constant potential of ~0.3V, this pins the gate of the upper JFET to
0.3V above the source of the lower JFET.

The tricky question is what is the effective channel lengths of the
two JFETs, and would this be a function of the overall DS voltage.

Rob

Rob,
I do not follow your argumentation here.
I always thought, the JFet is fully conducting with Vgs=0. So this is the
state it will be in naturally. Any positive Uds will cause the current Ids
to flow through the channel limited only by the channel resistance, when it
is higher 10V it will probably overheat. :-(
I think the gate voltage will stay pretty near zero, the more positive it
becomes the more the diode to S starts conducting. 300mV will never be
reached by itself.
Anyway Vgs higher 0.7V will damage the diode between Gate and Source.
You have to use this thing with gate voltages *below* 0.
Usually the gate connection is much closer to the source, which is also
indicated in the symbol.
|D
|-+
G |
-->|-+
|S

Go read up some more on FETs, before making false statements.

ciao Ban

 

[Robert Strand]

Go read up some more on FETs, before making false statements.

Perhaps you should do the test. Connect a JFET up with a resistor on the
drain and the source to ground. Look at what happens to the current when
the gate is grounded and when it is open.

Rob

 

[Ban]

Perhaps you should do the test. Connect a JFET up with a resistor on
the drain and the source to ground. Look at what happens to the
current when the gate is grounded and when it is open.

Rob

I just checked on an U404 from my stashbox, used a 7.2V LION-battery. with
the gate grounded I got 8.3mA. when I removed the connection the current
went up to 8.8mA. The gate voltage went to +133mV. Nothing spectacular,
actually absolutely expected.

Now I connected it to a simple power supply. with the gate open the
ripple(2Vpp) went directly onto the gate(because of the GD-capacitance I
suppose) and the current got modulated and actually much less.
I suppose because of the rectifying action of the GS-diode. In fact the gate
voltage went below 0 to around -0.5V. The current was around 6mA. But any
charge from your fingers etc. is influencing the Fet and I suspect it even
oscillating though I couldn't see and trigger to any HF. My scope samples at
only 25MHz. :-(

Now I tried to simulate with spice and it confirms with the short
experiment. I wonder what you have measured. Could you enlighten us ?

ciao Ban