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most appropriate high speed interface

J

Jan van Timpeln

Jan 1, 1970
0
Hello community,

I am a student of electrical engineering and in the course of a laboratory I
am currently designing a serdes chip and looking for an adequate interface
for the I/Os.
Power dissipation an chip space are the most relevant aspects. What I do is
a 10Gbit/s to 1 Gbit/s deserializing. On the input I am using LVDS signals,
so what would be an appropriate signalling on the output for 1Gbit/s
signals? Is it possible to transmit 1 Gbit/s single ended or do I need to
use differential signalling? Unfortunately that means double the pad number
and thus double chip space, but chip space is expensive.
Because the supply budget is limited I want a minimum on power dissipated at
the output buffers. What transmission standard would be advisable in that
respect?

Thank you very much in advance
Jan
 
J

Joseph2k

Jan 1, 1970
0
Jan said:
Hello community,

I am a student of electrical engineering and in the course of a laboratory
I am currently designing a serdes chip and looking for an adequate
interface for the I/Os.
Power dissipation an chip space are the most relevant aspects. What I do
is a 10Gbit/s to 1 Gbit/s deserializing. On the input I am using LVDS
signals, so what would be an appropriate signalling on the output for
1Gbit/s signals? Is it possible to transmit 1 Gbit/s single ended or do I
need to use differential signalling? Unfortunately that means double the
pad number and thus double chip space, but chip space is expensive.
Because the supply budget is limited I want a minimum on power dissipated
at the output buffers. What transmission standard would be advisable in
that respect?

Thank you very much in advance
Jan
If the design were for the most common 9.6 GB/s system then 8 to 1 is the
correct ratio. Or 4 to 1 or 16 to 1. At 16 to 1 single ended becomes
reasonable.
bad choice of follow up groups, this not a cad issue currently.
 
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