keith said:
You don' thave the latch in the library (which I suspected). It appears
that it's not smart enough to make one out of gates. Synplify would, but
bitch like hell doing it. There is a difference in tools.
Look at you IOBs. You may have an IOB that has an implied inversion. The
Xilinx IOBs were a littttle crazy with OE's, it wouldn't surprise me that
Altera had similar nonsense.
Thanks, I'm using Lattice as Altera doesnt seem to do the small parts,
it seems to use the synplify compiler for vhdl, but im just using the
schematic input method now as that seems to produce a fit in the small parts
ok.
Ive looked at the IOB on the data sheet and although they have inverted
outputs there is an xor with one input set high or low wich shld enable
selection of active low or active high outputs, both the 16v8 and 22v10 have
inverted outputs with an xor stage and one comes out inverted (q apears as
!q next to the relavent pin on the generated pinout diagram) the other
doesnt, im not sure if I should acount for that in my equations or not. i
think i might be able to figure it out from the jedec file, heck il probaly
end up just writing the jedec file.
Ive looked through the help files however many of the menus/icons I tried to
folow are greyed out wich probably means i need to go and look for more
modules to instal or something. it says something about a constraint editor
but the only option i have is to import a constraint file not edit it.
Colin =^.^=