- Jan 1, 1970
Perhaps something like...
(r,s, and q are standard_logic or standard_ulogic)
SRLatch: Process (S,R) -- Set dominant SR latch
IF s = '1' -- Set is dominant
THEN q <= '1';
ELSE IF r = '1'
THEN q <= '0';
I tried this, it cleverly sees theres a SR latch here and goes ahead and
uses one but then gives an error :-
'xxx devices do not have latch with both async set and reset. Fitter may
fail' (wich it does)
Il gues il stick to schematic entry as this seems to work although I still
havnt figured out how to stop it using negative logic on the outputs with