R
Rikard Bosnjakovic
- Jan 1, 1970
- 0
I have now solved the problem with the SR-latch, but I ran into a new
problem (which regards what I think is oscillation) instead.
Block-circuit for this project:
------------------------- --------------------------
1 | Triggers (S1, S2, MR) | ---> | SR-latches (trig-lock) | --->
------------------------- --------------------------
--------------------------------------------------------
1 ---> | OR-gate (made of two diodes and a pulldown resistor) | -->
--------------------------------------------------------
-------------------------------------
2 ---> | 555-trigger (monostable, 50 secs) | --->
-------------------------------------
----------------------------------------
2 ---> | 555-trigger (astable, 50% duty, 1Hz) | --->
----------------------------------------
-------------- ----------------
2 ---> | Mech relay | ---> | "Alarm-lamp" |
-------------- ----------------
Block 1 and 2 works as a charm separately, but when connecting them
together the both (actually one, but it triggers the other
automatically) 555:s just for a second and then the SR-latches gets
reset and they in turn resets the 555:s.
I don't have a scope so I can't dive down into the circuit and see
what happens and where, but I *think* the 555s cause a heavy
oscillation for the Vcc- and GND-rails that makes the RS-latch spike
on its R-input, and resets the outputs.
On play-hookey.com I read about the OR-gate I made (a DL-gate,
diode-logic gate) and it said that DL-gates sometimes can cause a lot
of distorsion in signals. Therefore I tried to use a "real" OR
(74LS32) instead.
The error did however remain for the 74LS32 as well. The 555s run a
second or two and the whole circuit gets reset. I tried to add a cap,
sized 100nF, to the output of the 74LS32 to see if it was the OR-gate
that wasn't able to fully source the 555. When I did this, the circuit
seemed to work fine. I'm not sure this means there was oscillation in
the circuit, since I haven't been able to dive down under the hood and
investigate because the lack of a scope.
Conclusion: If I use a proper OR-gate and add a cap, the circuit works.
But, the problem in doing this are two. First of all, I would rather
not waste a whole IC just for a simple gate, and second of all there
will most likely not be enough room on the veroboard which this
circuit will be residing after the prototyping is done. The space
where the veroboard will be is physically very limited, and that's the
reason I reached out for the solution to build an OR-gate of my own.
What I'm now wondering is if anyone, with the scenario above in mind,
can take a good guess in why the RS-latch is acting as it does when I
use my homebrewed OR-gate, or what on earth is resetting the circuit.
problem (which regards what I think is oscillation) instead.
Block-circuit for this project:
------------------------- --------------------------
1 | Triggers (S1, S2, MR) | ---> | SR-latches (trig-lock) | --->
------------------------- --------------------------
--------------------------------------------------------
1 ---> | OR-gate (made of two diodes and a pulldown resistor) | -->
--------------------------------------------------------
-------------------------------------
2 ---> | 555-trigger (monostable, 50 secs) | --->
-------------------------------------
----------------------------------------
2 ---> | 555-trigger (astable, 50% duty, 1Hz) | --->
----------------------------------------
-------------- ----------------
2 ---> | Mech relay | ---> | "Alarm-lamp" |
-------------- ----------------
Block 1 and 2 works as a charm separately, but when connecting them
together the both (actually one, but it triggers the other
automatically) 555:s just for a second and then the SR-latches gets
reset and they in turn resets the 555:s.
I don't have a scope so I can't dive down into the circuit and see
what happens and where, but I *think* the 555s cause a heavy
oscillation for the Vcc- and GND-rails that makes the RS-latch spike
on its R-input, and resets the outputs.
On play-hookey.com I read about the OR-gate I made (a DL-gate,
diode-logic gate) and it said that DL-gates sometimes can cause a lot
of distorsion in signals. Therefore I tried to use a "real" OR
(74LS32) instead.
The error did however remain for the 74LS32 as well. The 555s run a
second or two and the whole circuit gets reset. I tried to add a cap,
sized 100nF, to the output of the 74LS32 to see if it was the OR-gate
that wasn't able to fully source the 555. When I did this, the circuit
seemed to work fine. I'm not sure this means there was oscillation in
the circuit, since I haven't been able to dive down under the hood and
investigate because the lack of a scope.
Conclusion: If I use a proper OR-gate and add a cap, the circuit works.
But, the problem in doing this are two. First of all, I would rather
not waste a whole IC just for a simple gate, and second of all there
will most likely not be enough room on the veroboard which this
circuit will be residing after the prototyping is done. The space
where the veroboard will be is physically very limited, and that's the
reason I reached out for the solution to build an OR-gate of my own.
What I'm now wondering is if anyone, with the scenario above in mind,
can take a good guess in why the RS-latch is acting as it does when I
use my homebrewed OR-gate, or what on earth is resetting the circuit.