Opamp + capacitor gain circuit

[electronicsLearner77]

Trying the impact of capacitor in the opamp circuit as below


The equations of the opamp are
V1 - i1R2 -i1R1=Vout -> 1
The voltage at inverting input is same as non inverting input
V1 - i1R2 = 1/Cic dt -> 2
But there is no current in positive terminal as high impedance of the opamp, so i assume ic=0. What will be the behavior of the circuit?

 

[danadak]

You have a floating input (at low freq), so output unpredictable. Dominated by leakage current
and pickup and noise.....


If you are looking for a non inverting integrator :

Non-inverting integrator | Analog-integrated-circuits || Electronics Tutorial

Non-inverting integrator | Analog integrated circuits - Electronics Tutorial

www.electronics-tutorial.net

Regards, Dana.

 

[crutschow]

But there is no current in positive terminal as high impedance of the opamp, so i assume ic=0. What will be the behavior of the circuit?

Since there is no path for the op amp input bias current, the output will likely go to one of the supply rails and stay there.
The capacitor will have no other effect on the circuit response, even if you did provide a DC path.

 

[electronicsLearner77]

You have a floating input (at low freq), so output unpredictable. Dominated by leakage current
and pickup and noise.....

Can you please explain how did you find this?

 

[danadak]

Its not a "find" per se, but related to input bias current. If you cannot supply
the bias current with a DC path the input stage, bipolar, mosfet, jfet, whatever,
because its very hi Z, will take leakage current and Hi Z x inputleakage = drive the
input to a rail. Not only that, being very hi Z, the input will pickup stray signals,
like power line AC, so no telling exactly what its going to do. Also if the input is
driven outside its common mode range the input stage is unpredictable.

Regards

 

[Harald Kapp]

But there is no current in positive terminal as high impedance of the opamp, so i assume ic=0.

Here's your error.
For example MAX4478:

OP177:


Even a few nA of input current will over time charge the capacitor. So definitely I_in <> 0 A!

 

[danadak]

Not to complicate the discussion but the cap leakage current characteristics will also
determine if cap takes on a charge from bias current. Electrolytics, Tants, Ceramic pretty
leaky, film caps generally very low leakage. Complicating that Ceramics have a highly non-
linear relationship of V versus leakage.

Point of this is in high Z circuits one must pay attention to passive usage and
characteristics. even PCB track to track leakage can cause problems in high
performance DC applications.

Interesting ap notes when you have some time (your application not really applicable) :

https://www.edn.com/wp-content/uploads/2016/11/1982-10-13_EDN_Pease-capacitor-soakage.pdf

https://www.silabs.com/documents/public/application-notes/an1415-current_leakage_through_ceramic_capacitors.pdf

https://www.analog.com/en/technical-articles/passives-arent-really-so-passive-part-1-capacitors.html

https://www.analog.com/en/technical-articles/layout-for-precision-op-amps.html

https://ww1.microchip.com/downloads/en/AppNotes/01258B.pdf

Regards, Dana.