Optimizations for Inrush current

[M. Hamed]

I have a USB-powered board which draws a lot of inrush current (close
to 1A) on startup. This leads to problems with the USB interface with
the computer and also the voltage level droop seen by the devices on
the board. Now I am faced with the task of figuring out a way to solve
this problem but I have no clue over how to go about it.

The board has an FPGA, a microcontroller, SRAMs, EPROM, and plenty of
discreet components. No power sequencing is done and all the
regulators turn on at the same time. The board has a TPS2014 which
helps limiting inrush but seems is not enough.

How do I go about optimizing the values of bypass caps to reduce
inrush while maintaining their bypass function? Is there a way to
simulate that? Are there other ways? Power sequencing is a bit
difficult because the FPGA uses 3 supplies.

Thank you.

 

[linnix]

I have a USB-powered board which draws a lot of inrush current (close
to 1A) on startup. This leads to problems with the USB interface with
the computer and also the voltage level droop seen by the devices on
the board. Now I am faced with the task of figuring out a way to solve
this problem but I have no clue over how to go about it.

The board has an FPGA, a microcontroller, SRAMs, EPROM, and plenty of
discreet components. No power sequencing is done and all the
regulators turn on at the same time. The board has a TPS2014 which
helps limiting inrush but seems is not enough.

How do I go about optimizing the values of bypass caps to reduce
inrush while maintaining their bypass function? Is there a way to
simulate that? Are there other ways? Power sequencing is a bit
difficult because the FPGA uses 3 supplies.

Thank you.

What are the V & I on these 3 supplies? You should at least control
one or two of them?

 

[M. Hamed]

The voltages are: 3.3, 2.5, 1.2.

I'm clueless about two things:

1) How to measure current drawn from each regulator?

2) How to sequence power in hardware with no software control. Would
an RC delay + a transistor work?

Thanks.

 

[Eeyore]

I have a USB-powered board which draws a lot of inrush current (close
to 1A) on startup.

For how long ?

This leads to problems with the USB interface with
the computer and also the voltage level droop seen by the devices on
the board. Now I am faced with the task of figuring out a way to solve
this problem but I have no clue over how to go about it.

The board has an FPGA, a microcontroller, SRAMs, EPROM, and plenty of
discreet components. No power sequencing is done and all the
regulators turn on at the same time. The board has a TPS2014 which
helps limiting inrush but seems is not enough.

How do I go about optimizing the values of bypass caps to reduce
inrush while maintaining their bypass function? Is there a way to
simulate that? Are there other ways? Power sequencing is a bit
difficult because the FPGA uses 3 supplies.

The ICs themselves are unlikely to be responsible for that inrush current
I'd have thought.

How much capacitance do you have across the various rails. Way too much
I'll venture.

Graham

 

[amdx]

I have a USB-powered board which draws a lot of inrush current (close
to 1A) on startup. This leads to problems with the USB interface with
the computer and also the voltage level droop seen by the devices on
the board. Now I am faced with the task of figuring out a way to solve
this problem but I have no clue over how to go about it.

The board has an FPGA, a microcontroller, SRAMs, EPROM, and plenty of
discreet components. No power sequencing is done and all the
regulators turn on at the same time. The board has a TPS2014 which
helps limiting inrush but seems is not enough.

How do I go about optimizing the values of bypass caps to reduce
inrush while maintaining their bypass function? Is there a way to
simulate that? Are there other ways? Power sequencing is a bit
difficult because the FPGA uses 3 supplies.

Thank you.

I don't know if these inrush current limiters would be slow enough to
remove your glitch, but worth checking out, or waiting for others to
give their opinion. My only experience is replacing a smoked one in my
computer
power supply. Interesting devices!
http://www.ametherm.com/Inrush_Current/inrush_current_limiters_pcim.htm

Maybe this one?
http://www.ametherm.com/Data Sheets/SL10 30001.pdf
Mike

 

[Jamie]

At GenRad I used a resistor paralleled with a TRIAC.

...Jim Thompson

But Jim, that's to easy and cheap!.. can't you come up with
something that breaks the budget ?


http://webpages.charter.net/jamie_5"

 

[M. Hamed]

For how long ?

For about 500 us

How much capacitance do you have across the various rails. Way too much
I'll venture.

around 90 uF on the 5V main supply, and around 22 uF on the 3 other
supplies

 

[neon]

you can only t out of a USB 500ma so the boaed whatever it is has a bad design solution keep the USB active at all times mine PC is