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oscillation in high-voltage MOSFETS connected in series

W

Winfield Hill

Jan 1, 1970
0
continued OT from the thread, Looking for pulse-rated zener.

colin wrote...
Winfield Hill wrote ...

Yes thanks thats what i was asking, as both cases have the vds>20v
at high curent. Trying to think of a way of avoiding it yet still
using a more deterministic way of setting the peak voltage.

Actually i was wondering if a cascode mosfet arangement would behave
any better, again it might make it less noticable as the bottom device
would stay more in control of the current, although i would be worried
about this as long ago I had some nasty oscilations when i was trying
to make a high voltage power supply with several series mosfets (600v
mosfets were very limited at the time), but unfortunatly i never had
the time (or the experience back then) to get to the bottom of all
the diferent modes of oscilations.

Hmm, oscillation for a high-voltage string of MOSFETS in series,
due to the series connection, you think? As opposed to just the
bottom MOSFET by itself? How high was the FET operating current
when you observed oscillation?

Let's evaluate the scene.

For a series-connected MOSFET the current gain is unity from DC
to a frequency f_T = g_m / 2pi Ciss, where the gate capacitance
robs the ac signal current away from the FET's source path. For
a BJT, the transconductance gm = Ic/Vt = 40 Ic. It's lower for
power MOSFETs, g_m = Id/nVt in the subthreshold region, where
n = 3 to 5, according to my measurements. So here a MOSFET has
3 to 5x lower g_m than a BJT at the same current. Above the
FET's threshold gate voltage, where the currents are from 5 to
100% of the FET's maximum operating current, g_m still rises
with current, but at a much slower rate.

I would think the bottom line is, you need to work within say
20% or higher of the FET's maximum current to get its g_m, and
thus f_T, high enough to take part in serious RF oscillation.
While operation at such a high voltage and current is practical
for a few milliseconds, I imagine it'd create too much power
dissipation to do continuously.

This means most continuous linear use of power MOSFETs occurs
in the subthreshold region, where the g_m/Id ratio is higher,
but where the transistor's f_T remains low, say under 20MHz.

For example, I'm using fqd2n100 surface-mount 2A 1kV FETs in
a series-connected amplifier. At the maximum current of 4mA
with 400V across the FET, it dissipates about 1.6W, pushing the
junction temperature up by about 90C, which is as high as I'm
comfortable to go. This FET has Ciss = 400pF. At 4mA it has
g_m = 32mS, which means its f_T = 13MHz. Oops! that's getting
into a dangerous region. If I was using a similar MOSFET, with
heatsinks, at currents higher than 4mA, there could be trouble.
 
C

colin

Jan 1, 1970
0
Winfield Hill said:
continued OT from the thread, Looking for pulse-rated zener.

colin wrote...

Hmm, oscillation for a high-voltage string of MOSFETS in series,
due to the series connection, you think? As opposed to just the
bottom MOSFET by itself? How high was the FET operating current
when you observed oscillation?

Let's evaluate the scene.

For a series-connected MOSFET the current gain is unity from DC
to a frequency f_T = g_m / 2pi Ciss, where the gate capacitance
robs the ac signal current away from the FET's source path. For
a BJT, the transconductance gm = Ic/Vt = 40 Ic. It's lower for
power MOSFETs, g_m = Id/nVt in the subthreshold region, where
n = 3 to 5, according to my measurements. So here a MOSFET has
3 to 5x lower g_m than a BJT at the same current. Above the
FET's threshold gate voltage, where the currents are from 5 to
100% of the FET's maximum operating current, g_m still rises
with current, but at a much slower rate.

I would think the bottom line is, you need to work within say
20% or higher of the FET's maximum current to get its g_m, and
thus f_T, high enough to take part in serious RF oscillation.
While operation at such a high voltage and current is practical
for a few milliseconds, I imagine it'd create too much power
dissipation to do continuously.

This means most continuous linear use of power MOSFETs occurs
in the subthreshold region, where the g_m/Id ratio is higher,
but where the transistor's f_T remains low, say under 20MHz.

For example, I'm using fqd2n100 surface-mount 2A 1kV FETs in
a series-connected amplifier. At the maximum current of 4mA
with 400V across the FET, it dissipates about 1.6W, pushing the
junction temperature up by about 90C, which is as high as I'm
comfortable to go. This FET has Ciss = 400pF. At 4mA it has
g_m = 32mS, which means its f_T = 13MHz. Oops! that's getting
into a dangerous region. If I was using a similar MOSFET, with
heatsinks, at currents higher than 4mA, there could be trouble.

Aha I see, it might be that a cascode arangement would be stable.

In my case power disipation was not too much of an issue as the input was
pre regulated with simple scr stage but what was needed specificaly was a
very fast acting short circuit protection. so the output device had to
handle the full voltage at full current only for half a mains cycle or so.

I cant remember the exact layout now but the initial problem I had was that
too much of the transient apeared acros the botom device due to drain-gate
capacitance of the other devices. using a chain of capacitors large enough
meant loading the input/output too much to offer quick enough short circuit
current protection. so i tried to make the transient apear accross each
device as evenly as possible and compensate for any change/diference in
device stats with what seemed a fairly simple chain of resistors capacitors
etc. where I think each gate voltage was derived partly from a divider
between its drain and the lower fets source.

However I think there were too many paths basicaly so I just simply couldnt
understand what was going on and of course as soon as you atach a probe it
all changes, as soon as I got oscilation the things usualy went 'pop' fairly
quickly anyway becuase they all seemed to oscillate wildly and out of phase
and so peaked above their max vds.

I'm fairly sure this wasnt internal oscillation as I added capacitors where
i thought they would do good only to find that it just reduced the frequency
but made it more likly to oscillate. I think the chain of capacitors etc
basicaly formed a signal path in a ring like in a phase shift oscilator but
i just couldnt see it at the time.

I was trying to use much lower voltage fets (200v) as they were far more
robust than the almost available 600v devices but I gues it would of been
better to use a few dozen of those in parallel although I only had 4 at the
time and they were hard to get.

It was basicaly to help trouble shoot a problomatic SMPS/PFC design but that
problem went away first.

The only thing I have come acros that might explain it was a circuit for a
'chaotic oscillator' wich used cascoded fets.

I dare say now i could easily solve the problem with an aditiional 20+ years
experience (and of course easily done with a single fet now) but it was one
of those things you just strongly remember not to tackle anything like that
again lightly.

Its one of those things that makes electronics so chalenging and hard to put
down.

Colin =^.^=
 
W

Winfield Hill

Jan 1, 1970
0
colin wrote...
In my case power disipation was not too much of an issue as the input was
pre regulated with simple scr stage but what was needed specificaly was a
very fast acting short circuit protection. so the output device had to
handle the full voltage at full current only for half a mains cycle or so.

I cant remember the exact layout now but the initial problem I had was that
too much of the transient apeared acros the botom device due to drain-gate
capacitance of the other devices. using a chain of capacitors large enough
meant loading the input/output too much to offer quick enough short circuit
current protection. so i tried to make the transient apear accross each
device as evenly as possible and compensate for any change/diference in
device stats with what seemed a fairly simple chain of resistors capacitors
etc. where I think each gate voltage was derived partly from a divider
between its drain and the lower fets source.

However I think there were too many paths basicaly so I just simply couldnt
understand what was going on and of course as soon as you atach a probe it
all changes, as soon as I got oscilation the things usualy went 'pop' fairly
quickly anyway becuase they all seemed to oscillate wildly and out of phase
and so peaked above their max vds.

I'm fairly sure this wasnt internal oscillation as I added capacitors where
i thought they would do good only to find that it just reduced the frequency
but made it more likly to oscillate. I think the chain of capacitors etc
basicaly formed a signal path in a ring like in a phase shift oscilator but
i just couldnt see it at the time.

Yes. Power MOSFETs don't mind avalanche at all, provided you keep the
total power dissipation low enough that the junction temperature doesn't
go much above 200C. The datasheet's Transient Thermal Impedance curves
provide a quantitative way to evaluate the scene. But as you said, the
problem comes when the FET current is far too high during avalanche, and
part failure is a likely outcome.

I solved the probing problem for evaluating my 2500V series-connected FET
amplifier by making a spice model that I could trust, which meant modifying
the FET's model to work properly in the subthreshold region. And indeed,
when testing the fault condition of an instantaneous short circuit from a
full-scale output voltage, the bottom FET, which necessarily has different
gate impedances than the rest, avalanches. In my circuit the avalanche
duration is short and the current limited to a level that the FET doesn't
mind. Looking at the voltages, I was impressed how well the other stacked
FETs tracked, sharing the remaining voltage during the transient. I found
that relying on the huge charge on the FET's Ciss kept things under control
(i.e., adding a capacitive divider in parallel with the resistive one for
the gates would be a bad idea), and the change in gate voltages during the
transient was small. But, just as you experienced, I wasn't able to see
an easy way to get the bottom FET to take part in the well-behaved voltage
sharing. In high-power circuits where the avalanche would mean excessive
power dissipation, you'd have to find a solution to this issue.
 
F

Fred Bartoli

Jan 1, 1970
0
Winfield Hill said:
colin wrote...

I solved the probing problem for evaluating my 2500V series-connected FET
amplifier by making a spice model that I could trust, which meant modifying
the FET's model to work properly in the subthreshold region.

Nice.
Would you mind posting the original and final models?
Did you only changed the static behaviour or did you improved the parasitics
modeling too?
 
W

Winfield Hill

Jan 1, 1970
0
Fred Bartoli wrote...
Winfield Hill wrote...

Nice.
Would you mind posting the original and final models?
Did you only changed the static behaviour or did you improved the
parasitics modeling too?

The manufacturer's parasitics modeling is quite good, certainly far
better than needed for the reduced currents and speeds associated
with linear MOSFET circuits. But of special interest for low-power
linear use is the accuracy of the capacitance models, and these were
also pretty good. So the trick is to modify the FET model to include
the needed changes without damaging the properly-working part. I did
this by removing the gate capacitance from the intrinsic model and
inserting it back at the subcircuit level, outside of the modification
to fix the subthreshold problem. The fix involves adjusting VTO to
reduce the model's Vth to a low value, and adding a diode in series
with the gate to raise the voltage back up. The diode's voltage is
programmed by a current-controlled current source running from the
FET's source current. This nicely gives us the required exponential
characteristic, with the e^Vgs/nVt value "n" set to 5.5 with the diode
parameter N.

Here's the original model,

..SUBCKT FQD2N100 20 10 30
Rg 10 1 0.04
M1 2 1 3 3 DMOS L=1u W=1u
..MODEL DMOS NMOS(VTO=4.66 KP=1.9 LEVEL=3)
Cgs 1 3 380p
Rd 20 4 3.5
Dds 3 4 DDS
..MODEL DDS D(BV=1050 M=0.42 CJO=35p VJ=0.12)
Dbody 3 20 DBODY
..MODEL DBODY D(IS=2.8E-13 N=1.00 RS=0.005 EG=1.10 TT=520n)
Ra 4 2 3.5
Rs 3 5 0.024
Ls 5 30 2.6n
M2 1 8 6 6 INTER
E2 8 6 4 1 2
..MODEL INTER NMOS(VTO=0 KP=10 LEVEL=1)
CGDMAX 7 4 380p
RCGD 7 4 1E7
DGD 6 4 DGD
RDGD 4 6 1E7
..MODEL DGD D(M=0.52 CJO=380p VJ=0.12)
M3 7 9 1 1 INTER
E3 9 1 4 1 -2
..ENDS

And here's my modified model (assuming I found the right file).
I also corrected the leakage current by raising RDGD to 1G-ohm.

..SUBCKT FQD2N100xG 20 10 30
* see Motorola an1043 fig 2 for Cdg model
Rg 10 1 0.04
Dg 1 11 Dsubthres
..MODEL Dsubthres D (N=5.5 IS=0.1n EG=1.1)
F1 11 1 VSNS 1
M1 2 11 3 3 DMOS L=1u W=1u
..MODEL DMOS NMOS(VTO=2.0 KP=1.9 LEVEL=3)
Cgs 1 3 1p
Rd 20 4 3.5
Dds 15 4 DDS
..MODEL DDS D(BV=1050 M=0.42 CJO=35p VJ=0.12)
Dbody 15 20 DBODY
..MODEL DBODY D(IS=2.8E-13 N=1.00 RS=0.005 EG=1.10 TT=520n)
Ra 4 2 3.5
VSNS 3 15
Ciss 1 15 380p
Rs 15 5 0.024
Ls 5 30 2.6n
M2 1 8 6 6 INTER
E2 8 6 4 1 2
..MODEL INTER NMOS(VTO=0 KP=10 LEVEL=1)
CGDMAX 7 4 380p
RCGD 7 4 1E9
DGD 6 4 DGD
RDGD 4 6 1E9
..MODEL DGD D(M=0.52 CJO=380p VJ=0.12)
M3 7 9 1 1 INTER
E3 9 1 4 1 -2
..ENDS

You can read about the added-diode-approach in Steven M. Sandler's
article in Power Electronics Technology, May 2005. Hah, I had come
up with the basic scheme and used it to solve my problem 6 weeks
before Sandler's article came out. :>)
 
C

colin

Jan 1, 1970
0
Winfield Hill said:
Yes. Power MOSFETs don't mind avalanche at all, provided you keep the
total power dissipation low enough that the junction temperature doesn't
go much above 200C. The datasheet's Transient Thermal Impedance curves
provide a quantitative way to evaluate the scene. But as you said, the
problem comes when the FET current is far too high during avalanche, and
part failure is a likely outcome.

I solved the probing problem for evaluating my 2500V series-connected FET
amplifier by making a spice model that I could trust, which meant modifying
the FET's model to work properly in the subthreshold region. And indeed,
when testing the fault condition of an instantaneous short circuit from a
full-scale output voltage, the bottom FET, which necessarily has different
gate impedances than the rest, avalanches. In my circuit the avalanche
duration is short and the current limited to a level that the FET doesn't
mind. Looking at the voltages, I was impressed how well the other stacked
FETs tracked, sharing the remaining voltage during the transient. I found
that relying on the huge charge on the FET's Ciss kept things under control
(i.e., adding a capacitive divider in parallel with the resistive one for
the gates would be a bad idea), and the change in gate voltages during the
transient was small. But, just as you experienced, I wasn't able to see
an easy way to get the bottom FET to take part in the well-behaved voltage
sharing. In high-power circuits where the avalanche would mean excessive
power dissipation, you'd have to find a solution to this issue.

I would gues to do the series high voltage/power chain properly you would
need to use a driver circuit with feedback for each FET with its own
floating power supply to buffer the voltage from the divider... quite a bit
of extra complexity.

Or maybe just a simple low voltage pnp emiter follower across the
gate-source just to turn it off quicker under fualt condition would do fine,
but I only just thought of that ...

What speed does your amplifier have to slew at ? I assume its not that fast
so that the top FET cant keep up... <50v/us ?

Yes FET's are wondefull now compared to when I was first working on SMPS, at
that time we couldnt realy get the highest voltage ones (600v) to survive
fualt conditions reliably enough for 240v off line, although I was trying to
modify what was perhaps a rather poor design with slow fualt circuitry wich
was needing obselete specialy selected 1000v darlington bipolars to be
reliable. It was where I learned all about switch mode stuff ... certainly
felt like I was in well past the deep end but its a quick way to learn. The
driver ICs you can get now are so neat too with almost perfect fualt
condition handling. It almost seems too easy now.

Also when TI avalanche rated darlingtons first came out I found it hard to
beleive they were so robust.

Colin =^.^=
 
W

Winfield Hill

Jan 1, 1970
0
colin wrote...
Also when TI avalanche rated darlingtons first came out I found
it hard to beleive they were so robust.

Did you ever use any of them?
 
C

colin

Jan 1, 1970
0
Winfield Hill said:
colin wrote...

Did you ever use any of them?

Not in the comercial product as they ended up being quite a bit more
expensive, also they were a triple darlington and device disipation went up
significantly, I ended up redisigning the product to use a cheap but robust
non darlington bipolar with a new IC that had an integrated antisaturation
driver, worked quite well :)

I used one of the samples in a electronic ignition circuit as thats what
they were actualy marketing them at.

Colin =^.^=
 
T

Terry Given

Jan 1, 1970
0
colin said:
Not in the comercial product as they ended up being quite a bit more
expensive, also they were a triple darlington and device disipation went up
significantly, I ended up redisigning the product to use a cheap but robust
non darlington bipolar with a new IC that had an integrated antisaturation
driver, worked quite well :)

I used one of the samples in a electronic ignition circuit as thats what
they were actualy marketing them at.

Colin =^.^=

I started work at a drive company just after they stopped manufacturing
their last bipolar drive (1993). The BJTs were also triple darlingtons,
referred to as "tralingtons". The 600Arms drive was a beast, tralingtons
switching at 2kHz from a 700Vdc bus. All wired with cable and crimps.
The base drives supplied something like 100A.

Cheers
Terry
 
C

colin

Jan 1, 1970
0
Terry Given said:
I started work at a drive company just after they stopped manufacturing
their last bipolar drive (1993). The BJTs were also triple darlingtons,
referred to as "tralingtons". The 600Arms drive was a beast, tralingtons
switching at 2kHz from a 700Vdc bus. All wired with cable and crimps.
The base drives supplied something like 100A.

Cheers
Terry

Yeah, despite being a triple darlington its gain ends up quite low if you
have to drive it hard.

Colin =^.^=
 
M

Mike Monett

Jan 1, 1970
0
Terry Given wrote:

[...]
I started work at a drive company just after they stopped manufacturing
their last bipolar drive (1993). The BJTs were also triple darlingtons,
referred to as "tralingtons". The 600Arms drive was a beast, tralingtons
switching at 2kHz from a 700Vdc bus. All wired with cable and crimps.
The base drives supplied something like 100A.

Cheers
Terry

My hat's off to those of you brave enough to work on equipment like that. I
don't have the courage. But one thing I notice in these discussions of working
on high power is the absence of reference to flash hazards.

Since I have no intention of working anywhere near this stuff, I admit I have
not studied the applicable regulations. But for those who do live dangerously,
if you haven't studied the danger of flash arcs, here's one place to start:

"The Dangers of Arc Flash Incidents"

http://www.mt-online.com/articles/0204arcflash.cfm

Mike Monett
 
T

Terry Given

Jan 1, 1970
0
colin said:
Yeah, despite being a triple darlington its gain ends up quite low if you
have to drive it hard.

Colin =^.^=

I'll say! about 4. And they were very fragile c.f. IGBTs.

Cheers
Terry
 
T

Terry Given

Jan 1, 1970
0
Mike said:
Terry Given wrote:

[...]

I started work at a drive company just after they stopped manufacturing
their last bipolar drive (1993). The BJTs were also triple darlingtons,
referred to as "tralingtons". The 600Arms drive was a beast, tralingtons
switching at 2kHz from a 700Vdc bus. All wired with cable and crimps.
The base drives supplied something like 100A.

Cheers
Terry


My hat's off to those of you brave enough to work on equipment like that. I
don't have the courage. But one thing I notice in these discussions of working
on high power is the absence of reference to flash hazards.

I have never worked on really big stuff - only 480V <= 1MW.

fusing is quite important. Not to prevent the power electronics from
failing, but to keep the enclosure intact when it does.

Even so, a 15kJ DC bus can do a lot of damage.
Since I have no intention of working anywhere near this stuff, I admit I have
not studied the applicable regulations. But for those who do live dangerously,
if you haven't studied the danger of flash arcs, here's one place to start:

"The Dangers of Arc Flash Incidents"

http://www.mt-online.com/articles/0204arcflash.cfm

Mike Monett

5kJ/cm^2 is a fair ole chunk of energy density.


Cheers
Terry
 
M

Mike Monett

Jan 1, 1970
0
Terry Given wrote:

[...]
I have never worked on really big stuff - only 480V <= 1MW.

fusing is quite important. Not to prevent the power electronics from
failing, but to keep the enclosure intact when it does.

Even so, a 15kJ DC bus can do a lot of damage.
[...]


5kJ/cm^2 is a fair ole chunk of energy density.
Cheers
Terry

This hv stuff is really bad. Something can happen somewhere else that
exposes you to the full blast. Here's an example of what happens when you
hit 16,000 volts:

http://members.tripod.com/~StormTrooper_2/index2.htm

And here's some advanced stuff:

http://205.243.100.155/frames/longarc.htm

I'll stay with +/-15V, thank you very much:)

Mike Monett
 
F

Fred Bartoli

Jan 1, 1970
0
"Winfield Hill" <[email protected]_rowland-dotties-harvard-dot.s-edu> a écrit dans le
message de
<snipped good stuff>

Thanks a bunch.
 
R

Rich Grise

Jan 1, 1970
0
Terry Given wrote:
[...]
I have never worked on really big stuff - only 480V <= 1MW.
fusing is quite important. Not to prevent the power electronics from
failing, but to keep the enclosure intact when it does.
Even so, a 15kJ DC bus can do a lot of damage.
5kJ/cm^2 is a fair ole chunk of energy density.
This hv stuff is really bad. Something can happen somewhere else that
exposes you to the full blast. Here's an example of what happens when you
hit 16,000 volts:
http://members.tripod.com/~StormTrooper_2/index2.htm
And here's some advanced stuff:
http://205.243.100.155/frames/longarc.htm
I'll stay with +/-15V, thank you very much:)

When I was much younger and much stupider, I set myself up for an
opportunity for a show much like the guy in the first sequence, sans
audience except for my psycho buddy who had talked me into climbing
the tower with him. This was one of those Eiffel-tower style hiline
towers.

I don't remember the exact details - I was in the clutches of
acrophobia and peer pressure simultaneously, so I didn't know
what to do. Somehow or another, my buddy and I (I was in early
teens - yeah, I know - testosterone time!) got within arm's
reach of what must have been a medium-voltage feeder that
was subsidiary to the hi-line - it was still terribly high!
But, anyway, being the stupid teenage boy I was, I reached
out and grasped that big fat wire. It was about 3/4" diameter,
and just by looking it was easy to tell that it was insulated.
Like, it had, '33000V' silkscreened on the jacket.

And I _felt_ it. I don't know if it was magnetic or electrostatic,
but I literally _felt_ the 60Hz thrumming through the line, and
by induction or capacitation or whatever the phenomenon was,
I felt it in my hand.

That's some seriously high power/voltage/current we're dealing
with here. =:-O

Needless to say, I didn't get electrocuted. ;-)
 
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